Merge branch '2.4.x' into 2.5.x

* 2.4.x:
  base/dispatch.c: Check for XMM registers after CPUID probe.
  rand/noise.c: Fix foolish bug in the `getentropy' code.

diff --combined base/dispatch.c
index 9f2ac71,b281ec3..bea97b4
--- 1/base/dispatch.c
--- 2/base/dispatch.c
+++ b/base/dispatch.c
@@@ -46,10 -46,7 +46,10 @@@
  #  define EFLAGS_ID (1u << 21)
  #  define CPUID1D_SSE2 (1u << 26)
  #  define CPUID1D_FXSR (1u << 24)
 +#  define CPUID1C_PCLMUL (1u << 1)
 +#  define CPUID1C_SSSE3 (1u << 9)
  #  define CPUID1C_AESNI (1u << 25)
 +#  define CPUID1C_AVX (1u << 28)
  #  define CPUID1C_RDRAND (1u << 30)
  
  struct cpuid { unsigned a, b, c, d; };
@@@ -284,15 -281,13 +284,15 @@@ static unsigned hwcaps = 0
        _(ARM_NEON, "arm:neon")                                         \
        _(ARM_V4, "arm:v4")                                             \
        _(ARM_D32, "arm:d32")                                           \
 -      _(ARM_AES, "arm:aes")
 +      _(ARM_AES, "arm:aes")                                           \
 +      _(ARM_PMULL, "arm:pmull")
  #endif
  #if CPUFAM_ARM64
  #  define WANTAUX(_)                                                  \
        WANT_AT_HWCAP(_)
  #  define CAPMAP(_)                                                   \
 -      _(ARM_AES, "arm:aes")
 +      _(ARM_AES, "arm:aes")                                           \
 +      _(ARM_PMULL, "arm:pmull")
  #endif
  
  /* Build the bitmask for `hwcaps' from the `CAPMAP' list. */
@@@ -406,13 -401,9 +406,13 @@@ static void probe_hwcaps(void
  #  ifdef HWCAP2_AES
    if (probed.hwcap2 & HWCAP2_AES) hw |= HF_ARM_AES;
  #  endif
 +#  ifdef HWCAP2_PMULL
 +  if (probed.hwcap2 & HWCAP2_PMULL) hw |= HF_ARM_PMULL;
 +#  endif
  #endif
  #if CPUFAM_ARM64
    if (probed.hwcap & HWCAP_AES) hw |= HF_ARM_AES;
 +  if (probed.hwcap & HWCAP_PMULL) hw |= HF_ARM_PMULL;
  #endif
  
    /* Store the bitmask of features we probed for everyone to see. */
@@@ -547,22 -538,13 +547,22 @@@ int cpu_feature_p(int feat
    switch (feat) {
  #if CPUFAM_X86 || CPUFAM_AMD64
      CASE_CPUFEAT(X86_SSE2, "x86:sse2",
-                xmm_registers_available_p() &&
-                cpuid_features_p(CPUID1D_SSE2, 0));
+                cpuid_features_p(CPUID1D_SSE2, 0) &&
+                xmm_registers_available_p());
      CASE_CPUFEAT(X86_AESNI, "x86:aesni",
-                xmm_registers_available_p() &&
-                cpuid_features_p(CPUID1D_SSE2, CPUID1C_AESNI));
+                cpuid_features_p(CPUID1D_SSE2, CPUID1C_AESNI) &&
+                xmm_registers_available_p());
      CASE_CPUFEAT(X86_RDRAND, "x86:rdrand",
                 cpuid_features_p(0, CPUID1C_RDRAND));
-                xmm_registers_available_p() &&
-                cpuid_features_p(0, CPUID1C_AVX));
 +    CASE_CPUFEAT(X86_AVX, "x86:avx",
-                xmm_registers_available_p() &&
-                cpuid_features_p(0, CPUID1C_SSSE3));
++               cpuid_features_p(0, CPUID1C_AVX) &&
++               xmm_registers_available_p());
 +    CASE_CPUFEAT(X86_SSSE3, "x86:ssse3",
-                xmm_registers_available_p() &&
-                cpuid_features_p(0, CPUID1C_PCLMUL));
++               cpuid_features_p(0, CPUID1C_SSSE3) &&
++               xmm_registers_available_p());
 +    CASE_CPUFEAT(X86_PCLMUL, "x86:pclmul",
++               cpuid_features_p(0, CPUID1C_PCLMUL) &&
++               xmm_registers_available_p());
  #endif
  #ifdef CAPMAP
  #  define FEATP__CASE(feat, tok)                                      \