mdw@git.distorted.org.uk Git - ssr/blob - StraySrc/Libraries/Core/header

   1 ;
   2 ; header
   3 ;
   4 ; Standard header
   5 ;
   6 ; © 1994-1998 Straylight
   7 ;
   8
   9 ;----- Licensing note -------------------------------------------------------
  10 ;
  11 ; This file is part of Straylight's core library (corelib).
  12 ;
  13 ; Corelib is free software; you can redistribute it and/or modify
  14 ; it under the terms of the GNU General Public License as published by
  15 ; the Free Software Foundation; either version 2, or (at your option)
  16 ; any later version.
  17 ;
  18 ; Corelib is distributed in the hope that it will be useful,
  19 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
  20 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21 ; GNU General Public License for more details.
  22 ;
  23 ; You should have received a copy of the GNU General Public License
  24 ; along with Corelib.  If not, write to the Free Software Foundation,
  25 ; 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  26
  27                 [       :LNOT::DEF:header__dfn
  28                 GBLL    header__dfn
  29
  30 ;----- Register names -------------------------------------------------------
  31
  32 ; --- The standard ones ---
  33
  34 R0              RN      0
  35 R1              RN      1
  36 R2              RN      2
  37 R3              RN      3
  38 R4              RN      4
  39 R5              RN      5
  40 R6              RN      6
  41 R7              RN      7
  42 R8              RN      8
  43 R9              RN      9
  44 R10             RN      10
  45 R11             RN      11
  46 R12             RN      12
  47 R13             RN      13
  48 R14             RN      14
  49 R15             RN      15
  50
  51 ; --- Standard pseudonyms ---
  52
  53 SP              RN      13
  54 LR              RN      14
  55 PC              RN      15
  56
  57 ; --- Lowercase version ---
  58
  59 r0              RN      0
  60 r1              RN      1
  61 r2              RN      2
  62 r3              RN      3
  63 r4              RN      4
  64 r5              RN      5
  65 r6              RN      6
  66 r7              RN      7
  67 r8              RN      8
  68 r9              RN      9
  69 r10             RN      10
  70 r11             RN      11
  71 r12             RN      12
  72 r13             RN      13
  73 r14             RN      14
  74 r15             RN      15
  75
  76 ; --- APCS names ---
  77
  78 a1              RN      0
  79 a2              RN      1
  80 a3              RN      2
  81 a4              RN      3
  82 v1              RN      4
  83 v2              RN      5
  84 v3              RN      6
  85 v4              RN      7
  86 v5              RN      8
  87 v6              RN      9
  88 sl              RN      10
  89 fp              RN      11
  90 ip              RN      12
  91 sp              RN      13
  92 lr              RN      14
  93 pc              RN      15
  94
  95 ; --- Floating point register names ---
  96
  97 F0              FN      0
  98 F1              FN      1
  99 F2              FN      2
 100 F3              FN      3
 101 F4              FN      4
 102 F5              FN      5
 103 F6              FN      6
 104 F7              FN      7
 105
 106 ; --- Lowercase floating point names ---
 107
 108 f0              FN      0
 109 f1              FN      1
 110 f2              FN      2
 111 f3              FN      3
 112 f4              FN      4
 113 f5              FN      5
 114 f6              FN      6
 115 f7              FN      7
 116
 117 ;----- ARM processor flags --------------------------------------------------
 118
 119 ; --- Processor flags ---
 120
 121 FIQ_disable     EQU     1<<26
 122 IRQ_disable     EQU     1<<27
 123
 124 V_flag          EQU     1<<28
 125 C_flag          EQU     1<<29
 126 Z_flag          EQU     1<<30
 127 N_flag          EQU     1<<31
 128
 129 ; --- Processor modes ---
 130
 131 USR_mode        EQU     0
 132 FIQ_mode        EQU     1
 133 IRQ_mode        EQU     2
 134 SVC_mode        EQU     3
 135
 136 ;----- Various useful macros ------------------------------------------------
 137
 138 ; --- Macro: PAD ---
 139 ;
 140 ; Arguments:    len == length to pad to
 141 ;               string == the string to write
 142 ;               byte == byte to fill with (default == 0)
 143 ;
 144 ; Use:          Writes a string out, and pads it to a given length.  If the
 145 ;               string is too long, it gets truncated.
 146
 147
 148                 MACRO
 149 $label          PAD     $len,$string,$byte
 150                 LCLA    b
 151                 LCLA    i
 152
 153                 IF      "$len"=""
 154 b               SETA    0
 155                 ELSE
 156 b               SETA    $byte
 157                 ENDIF
 158
 159                 ALIGN
 160 $label
 161 i               SETA    :LEN: "$string"
 162
 163                 IF      i>$len
 164                 DCB     "$string" :LEFT: $len
 165                 ELSE
 166                 DCB     "$string"
 167                 WHILE   i<$len
 168                 DCB     b
 169 i               SETA    i+1
 170                 WEND
 171                 ENDIF
 172
 173                 MEND
 174
 175 ; --- Macro: BARRIER ---
 176 ;
 177 ; Arguments:    --
 178 ;
 179 ; Use:          Inserts a cache barrier in the code (SWI &FF0000) for
 180 ;               executing dynamically-generated code.
 181
 182                 MACRO
 183 $label          BARRIER
 184                 ALIGN
 185 $label
 186 ;               SWI     &F00000                 ;Covered by NDA currently
 187                 MEND
 188
 189 ;----- That's all, folks ----------------------------------------------------
 190
 191                 ]
 192
 193                 END
 194
 195