4 ### Generate input script and expected output for bit manipulation,
5 ### particularly 64-bit arithmetic.
10 if SYS
.version_info
>= (3,): xrange = range
16 FMT
= "%%0%dx" %
(WD
/4)
18 def rol(x
, n
): return ((x
<< n
) |
(x
>> (WD
- n
))) & MASK
19 def ror(x
, n
): return ((x
>> n
) |
(x
<< (WD
- n
))) & MASK
21 class BaseVector (object):
24 def newseed(me
, seed
):
26 me
._all
.append((seed
, me
._curr
))
27 def _append(me
, *args
):
28 if len(args
) != len(me
._REGS
):
29 raise TypeError("expected %d arguments" %
len(me
._REGS
))
33 print("[%s]" % me
._NAME
)
34 for seed
, vv
in me
._all
:
36 print(";;; seed = 0x%08x" % seed
)
39 for r
, x
in zip(me
._REGS
, v
): print("%s = %s" %
(r
, me
._RFMT
[r
] % x
))
41 class ShiftVector (BaseVector
):
42 _REGS
= ["x", "n", "z"]
43 _RFMT
= { "x": FMT
, "n": "%d", "z": FMT
}
45 for i
in xrange(NVEC
):
46 x
= r
.randrange(LIMIT
)
47 n
= r
.randrange(70)%WD
51 x
= r
.randrange(LIMIT
)
53 me
._append(x
, WD
/2, z
)
54 class LSLVector (ShiftVector
):
56 def _op(me
, x
, n
): return (x
<< n
)&MASK
57 class LSRVector (ShiftVector
):
59 def _op(me
, x
, n
): return (x
>> n
)&MASK
60 class ROLVector (ShiftVector
):
62 def _op(me
, x
, n
): return rol(x
, n
)
63 class RORVector (ShiftVector
):
65 def _op(me
, x
, n
): return ror(x
, n
)
67 class ArithVector (BaseVector
):
68 _REGS
= ["x", "y", "z"]
69 _RFMT
= { "x": FMT
, "y": FMT
, "z": FMT
}
71 for i
in xrange(NVEC
):
72 x
= r
.randrange(LIMIT
)
73 y
= r
.randrange(LIMIT
)
76 class AddVector (ArithVector
):
78 def _op(me
, x
, y
): return (x
+ y
)&MASK
79 class SubVector (ArithVector
):
81 def _op(me
, x
, y
): return (x
- y
)&MASK
83 VECS
= [LSLVector(), LSRVector(), ROLVector(), RORVector(),
84 AddVector(), SubVector()]
86 for arg
in SYS
.argv
[1:]:
87 if arg
== "-": seed
= R
.SystemRandom().randrange(1 << 32)
88 else: seed
= int(arg
, 0)
90 for v
in VECS
: v
.newseed(seed
); v
.add(r
)
92 print(";;; -*-conf-*- Test vectors for 64-bit arithmetic macros")
93 print(";;; [generated]")
95 for v
in VECS
: v
.write()