1 /// -*- mode: asm; asm-comment-char: ?/ -*-
3 /// Fancy SIMD implementation of ChaCha for ARM
5 /// (c) 2016 Straylight/Edgeware
8 ///----- Licensing notice ---------------------------------------------------
10 /// This file is part of Catacomb.
12 /// Catacomb is free software; you can redistribute it and/or modify
13 /// it under the terms of the GNU Library General Public License as
14 /// published by the Free Software Foundation; either version 2 of the
15 /// License, or (at your option) any later version.
17 /// Catacomb is distributed in the hope that it will be useful,
18 /// but WITHOUT ANY WARRANTY; without even the implied warranty of
19 /// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 /// GNU Library General Public License for more details.
22 /// You should have received a copy of the GNU Library General Public
23 /// License along with Catacomb; if not, write to the Free
24 /// Software Foundation, Inc., 59 Temple Place - Suite 330, Boston,
25 /// MA 02111-1307, USA.
27 ///--------------------------------------------------------------------------
31 #include "asm-common.h"
38 ///--------------------------------------------------------------------------
41 FUNC(chacha_core_arm_neon)
43 // Arguments are in registers.
44 // r0 is the number of rounds to perform
45 // r1 points to the input matrix
46 // r2 points to the output matrix
48 // First job is to slurp the matrix into the SIMD registers. vldm
49 // and vstm work on word-aligned data, so this is fine.
53 // [ 8 9 10 11] (c, q10)
54 // [12 13 14 15] (d, q11)
56 // We need a copy for later. Rather than waste time copying them by
57 // hand, we'll use the three-address nature of the instruction set.
58 // But this means that the main loop is offset by a bit.
59 vldmia r1, {QQ(q12, q15)}
61 // a += b; d ^= a; d <<<= 16
66 // c += d; b ^= c; b <<<= 12
67 vadd.u32 q10, q14, q11
73 // Apply (the rest of) a column quarterround to each of the columns
74 // simultaneously. Alas, there doesn't seem to be a packed word
75 // rotate, so we have to synthesize it.
77 // a += b; d ^= a; d <<<= 8
83 // c += d; b ^= c; b <<<= 7
84 vadd.u32 q10, q10, q11
85 vext.32 q11, q11, q11, #3
87 vext.32 q10, q10, q10, #2
91 // The not-quite-transpose conveniently only involves reordering
92 // elements of individual rows, which can be done quite easily. It
93 // doesn't involve any movement of elements between rows, or even
94 // renaming of the rows.
96 // [ 0 1 2 3] [ 0 1 2 3] (a, q8)
97 // [ 4 5 6 7] --> [ 5 6 7 4] (b, q9)
98 // [ 8 9 10 11] [10 11 8 9] (c, q10)
99 // [12 13 14 15] [15 12 13 14] (d, q11)
101 // The reorderings have for the most part been pushed upwards to
103 vext.32 q9, q9, q9, #1
105 // Apply the diagonal quarterround to each of the columns
108 // a += b; d ^= a; d <<<= 16
113 // c += d; b ^= c; b <<<= 12
114 vadd.u32 q10, q10, q11
119 // a += b; d ^= a; d <<<= 8
123 vsri.u32 q11, q0, #24
125 // c += d; b ^= c; b <<<= 7
126 vadd.u32 q10, q10, q11
127 vext.32 q11, q11, q11, #1
129 vext.32 q10, q10, q10, #2
133 // Finally finish off undoing the transpose, and we're done for this
134 // doubleround. Again, most of this was done above so we don't have
135 // to wait for the reorderings.
136 vext.32 q9, q9, q9, #3
138 // Decrement the loop counter and see if we should go round again.
142 // Do the first part of the next round because this loop is offset.
144 // a += b; d ^= a; d <<<= 16
149 // c += d; b ^= c; b <<<= 12
150 vadd.u32 q10, q10, q11
157 // Almost there. Firstly the feedfoward addition.
158 9: vadd.u32 q8, q8, q12
160 vadd.u32 q10, q10, q14
161 vadd.u32 q11, q11, q15
163 // And now we write out the result.
164 vstmia r2, {QQ(q8, q11)}
166 // And with that, we're done.
171 ///----- That's all, folks --------------------------------------------------