From d0866297d1ea69ae7e0ff53e8e642be02a50917f Mon Sep 17 00:00:00 2001 From: Fredrik Fornwall Date: Wed, 19 Oct 2016 19:17:57 -0400 Subject: [PATCH] fftw: Update from 3.3.4 to 3.3.5 --- packages/fftw/build.sh | 13 +++--- packages/fftw/cross-compilation.patch | 88 +++++++++++++++++++++++++++++++++++ 2 files changed, 94 insertions(+), 7 deletions(-) create mode 100644 packages/fftw/cross-compilation.patch diff --git a/packages/fftw/build.sh b/packages/fftw/build.sh index d47af0e7..f0d81abd 100644 --- a/packages/fftw/build.sh +++ b/packages/fftw/build.sh @@ -1,11 +1,10 @@ TERMUX_PKG_HOMEPAGE=http://www.fftw.org/ TERMUX_PKG_DESCRIPTION="Library for computing the Discrete Fourier Transform (DFT) in one or more dimensions" -TERMUX_PKG_VERSION=3.3.4 +TERMUX_PKG_VERSION=3.3.5 TERMUX_PKG_SRCURL=http://www.fftw.org/fftw-${TERMUX_PKG_VERSION}.tar.gz -# --enable-neon requires fftw to be built with single precision, so do not enable -#termux_step_pre_configure () { -#if [ "$TERMUX_HOST_PLATFORM" = "arm-linux-androideabi" ]; then -#TERMUX_PKG_EXTRA_CONFIGURE_ARGS+=" --enable-neon" -#fi -#} +termux_step_pre_configure () { + # We are patching autoconf.ac. + cd $TERMUX_PKG_SRCDIR + autoreconf +} diff --git a/packages/fftw/cross-compilation.patch b/packages/fftw/cross-compilation.patch new file mode 100644 index 00000000..a67fa51a --- /dev/null +++ b/packages/fftw/cross-compilation.patch @@ -0,0 +1,88 @@ +From https://github.com/FFTW/fftw3/issues/73 + +diff --git a/configure.ac b/configure.ac +index 83a295f..51d290a 100644 +--- a/configure.ac ++++ b/configure.ac +@@ -212,11 +212,21 @@ if test "$have_neon" = "yes"; then + fi + AM_CONDITIONAL(HAVE_NEON, test "$have_neon" = "yes") + +-AC_ARG_ENABLE(armv8cyclecounter, [AC_HELP_STRING([--enable-armv8cyclecounter],[enable the cycle counter on ARMv8 ; require enabling in kernel mode, see ])], have_armv8cyclecounter=$enableval) ++AC_ARG_ENABLE(armv8cyclecounter, [AC_HELP_STRING([--enable-armv8cyclecounter],[enable the cycle counter on ARMv8 via the PMCCNTR_EL0 register. Requires enabling in kernel mode, see ])], have_armv8cyclecounter=$enableval) + if test "$have_armv8cyclecounter"x = "yes"x; then + AC_DEFINE(HAVE_ARMV8CC,1,[Define if you have enabled the cycle counter on ARMv8]) + fi + ++AC_ARG_ENABLE(armv8-cntvct-el0, [AC_HELP_STRING([--enable-armv8-cntvct-el0],[enable the cycle counter on ARMv8 via the CNTVCT_EL0 register])], have_armv8cntvctel0=$enableval) ++if test "$have_armv8cntvctel0"x = "yes"x; then ++ AC_DEFINE(HAVE_ARMV8_CNTVCT_EL0,1,[Define if you have enabled the CNTVCT_EL0 cycle counter on ARMv8]) ++fi ++ ++AC_ARG_ENABLE(armv7a-cntvct, [AC_HELP_STRING([--enable-armv7a-cntvct],[enable the cycle counter on Armv7a via the CNTVCT register])], have_armv7acntvct=$enableval) ++if test "$have_armv7acntvct"x = "yes"x; then ++ AC_DEFINE(HAVE_ARMV7A_CNTVCT,1,[Define if you have enabled the CNTVCT cycle counter on ARMv7a]) ++fi ++ + AC_ARG_ENABLE(generic-simd128, [AC_HELP_STRING([--enable-generic-simd128],[enable generic (gcc) 128-bit SIMD optimizations])], have_generic_simd128=$enableval, have_generic_simd128=no) + if test "$have_generic_simd128" = "yes"; then + AC_DEFINE(HAVE_GENERIC_SIMD128,1,[Define to enable generic (gcc) 128-bit SIMD optimizations.]) +@@ -719,36 +729,6 @@ AM_CONDITIONAL(OPENMP, test "$enable_openmp" = "yes") + AM_CONDITIONAL(SMP, test "$enable_threads" = "yes" -o "$enable_openmp" = "yes") + AM_CONDITIONAL(COMBINED_THREADS, test x"$with_combined_threads" = xyes) + +- +-dnl ----------------------------------------------------------------------- +-dnl Check for not-always-available (not quite) cycle counters +-case "${host_cpu}" in +- armv7*) +- AC_MSG_CHECKING([armv7a has 64 bits readable CNTVCT]) +- AC_RUN_IFELSE( +- [AC_LANG_PROGRAM([[#include ]], +- [[uint32_t Rt, Rt2 = 0;asm volatile("mrrc p15, 1, %0, %1, c14" : "=r"(Rt), "=r"(Rt2));]] +- )], +- [AC_DEFINE(ARMV7A_HAS_CNTCVT,1,[Define if CNTVCT is 64 bits readable on armv7a ]) +- AC_MSG_RESULT([yes])], +- [AC_MSG_RESULT([no])] +- ) +- ;; +- aarch64) +- AC_MSG_CHECKING([armv8 has 64 bits readable CNTVCT_EL0]) +- AC_RUN_IFELSE( +- [AC_LANG_PROGRAM([[#include ]], +- [[uint64_t Rt;asm volatile("mrs %0, CNTVCT_EL0" : "=r" (Rt));]] +- )], +- [AC_DEFINE(ARMV8_HAS_CNTCVT_EL0,1,[Define if CNTVCT_EL0 is 64 bits readable on armv8 ]) +- AC_MSG_RESULT([yes])], +- [AC_MSG_RESULT([no])] +- ) +- ;; +- *) +- ;; +-esac +- + dnl ----------------------------------------------------------------------- + + AC_MSG_CHECKING([whether a cycle counter is available]) +diff --git a/kernel/cycle.h b/kernel/cycle.h +index 873e92e..781792c 100644 +--- a/kernel/cycle.h ++++ b/kernel/cycle.h +@@ -515,7 +515,7 @@ INLINE_ELAPSED(inline) + #endif + #endif /* HAVE_MIPS_ZBUS_TIMER */ + +-#if defined(__ARM_ARCH_7A__) && defined(ARMV7A_HAS_CNTCVT) ++#if defined(__ARM_ARCH_7A__) && defined(ARMV7A_HAS_CNTVCT) + typedef uint64_t ticks; + static inline ticks getticks(void) + { +@@ -527,7 +527,7 @@ INLINE_ELAPSED(inline) + #define HAVE_TICK_COUNTER + #endif + +-#if defined(__aarch64__) && defined(ARMV8_HAS_CNTCVT_EL0) && !defined(HAVE_ARMV8CC) ++#if defined(__aarch64__) && defined(HAVE_ARMV8_CNTVCT_EL0) && !defined(HAVE_ARMV8CC) + typedef uint64_t ticks; + static inline ticks getticks(void) + { -- 2.11.0