;
; rdump.s
;
; Displays a register dump (sends it to VDUStream)
;
; © 1994-1998 Straylight
;

;----- Licensing note -------------------------------------------------------
;
; This file is part of Straylight's core libraries (corelib)
;
; Corelib is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 2, or (at your option)
; any later version.
;
; Corelib is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with Corelib.  If not, write to the Free Software Foundation,
; 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.

;----- Standard header ------------------------------------------------------

		GET	libs:header
		GET	libs:swis

;----- Main code ------------------------------------------------------------

		AREA	|Debug$$Code|,CODE,READONLY

; --- stream_regDump ---
;
; On entry:	R0 == pointer to saved R0-R15
;		R13 == pointer to full descending stack
;
; On exit:	R0-R14 corrupted
;
; Use:		Displays a register dump.

		EXPORT	stream_regDump
stream_regDump	ROUT

		STMFD	R13!,{R14}		;Save the link register

		; --- Start the main display loop ---

		MOV	R12,R0			;Keep pointer to dump block
		ADR	R11,stream__regNames	;Point to register name tbl
		MOV	R10,#0			;Which register we're on

		; --- Display a register ---

00		ADD	R0,R11,R10,LSL #2	;Point to the string
		SWI	Stream_Write0		;Display register name
		SWI	Stream_WriteS		;Display immediate string
		DCB	" == &",0		;A separater string
		LDR	R0,[R12,R10,LSL #2]	;Load the register value
		SWI	Stream_WriteH32		;Display register value
		SWI	Stream_WriteS		;Display more immediate
		DCB	"   ",0			;Just some spaces
		ADD	R10,R10,#1		;Increment register count
		TST	R10,#3			;Now a multiple of 4?
		SWIEQ	Stream_NewLine		;Yes -- new line then
		CMP	R10,#16			;Finished all registers?
		BLT	%00stream_regDump	;No -- do some more then

		; --- Now display R14 and R15 with PSR bits testually ---

		SWI	Stream_NewLine		;Another newline
		SWI	Stream_WriteS		;Display immediate stuff
		DCB	"R14 == &",0
		LDR	R9,[R12,#14*4]		;Load the R14 value
		BL	stream__psr		;Display all the PSR bits
		SWI	Stream_NewLine		;Another newline
		SWI	Stream_WriteS		;Display immediate stuff
		DCB	" PC == &",0
		LDR	R9,[R12,#15*4]		;Load the PC value
		BL	stream__psr		;Display all the PSR bits
		SWI	Stream_NewLine		;Another newline
		SWI	Stream_NewLine		;And one more for luck
		LDMFD	R13!,{PC}^		;Return to caller

stream__regNames
		DCB	" R0",0
		DCB	" R1",0
		DCB	" R2",0
		DCB	" R3",0
		DCB	" R4",0
		DCB	" R5",0
		DCB	" R6",0
		DCB	" R7",0
		DCB	" R8",0
		DCB	" R9",0
		DCB	"R10",0
		DCB	"R11",0
		DCB	"R12",0
		DCB	"R13",0
		DCB	"R14",0
		DCB	" PC",0

; --- stream__psr ---
;
; On entry:	R9 == value to display
;
; On exit:	R0-R12 corrupted, maybe
;
; Use:		Displays R9 with PSR bits stripped away, and then with
;		all the PSR bits described too.

stream__psr	ROUT

		STMFD	R13!,{R14}		;Save the link register
		BIC	R0,R9,#&FC000003	;Get the PC bits only
		SWI	Stream_WriteH32		;Display them in hex

		SWI	Stream_WriteS		;Some more spaces
		DCB	", flags == ",0
		MOV	R0,#'N'			;First do the `N' flag
		TST	R9,#N_flag		;Is it set
		ORREQ	R0,R0,#&20		;No -- force to lower case
		SWI	Stream_WriteT8		;Display the character
		MOV	R0,#'Z'			;First do the `N' flag
		TST	R9,#Z_flag		;Is it set
		ORREQ	R0,R0,#&20		;No -- force to lower case
		SWI	Stream_WriteT8		;Display the character
		MOV	R0,#'C'			;First do the `N' flag
		TST	R9,#C_flag		;Is it set
		ORREQ	R0,R0,#&20		;No -- force to lower case
		SWI	Stream_WriteT8		;Display the character
		MOV	R0,#'V'			;First do the `N' flag
		TST	R9,#V_flag		;Is it set
		ORREQ	R0,R0,#&20		;No -- force to lower case
		SWI	Stream_WriteT8		;Display the character

		SWI	Stream_WriteS		;Yet more stuff
		DCB	", mode == ",0
		ADR	R0,stream__modes	;Point to the mode strings
		AND	R14,R9,#3		;Get the mode bits
		ADD	R0,R0,R14,LSL #2	;Point to the correct string
		SWI	Stream_Write0		;Display the mode setting

		TST	R9,#IRQ_disable		;Is the IRQ bit on or off?
		ADREQ	R0,stream__irqOn	;If off, point to message
		SWIEQ	Stream_Write0		;And display the string
		TST	R9,#FIQ_disable		;Is the FIQ bit on or off?
		ADREQ	R0,stream__fiqOn	;If off, point to message
		SWIEQ	Stream_Write0		;And display the string
		LDMFD	R13!,{PC}^		;Return to caller

stream__modes	DCB	"USR",0
		DCB	"FIQ",0
		DCB	"IRQ",0
		DCB	"SVC",0

stream__irqOn	DCB	", IRQ",0
stream__fiqOn	DCB	", FIQ",0

;----- That's all, folks ----------------------------------------------------

		END