;
; dump
;
; Dump a register block
;
; © 1994-1998 Straylight
;

;----- Licensing note -------------------------------------------------------
;
; This file is part of Straylight's core library (corelib).
;
; Corelib is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 2, or (at your option)
; any later version.
;
; Corelib is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with Corelib.  If not, write to the Free Software Foundation,
; 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.

; dump
;
; Standard routine - displays contents of a register save block.  May be
; used in SVC mode.
;
; Parameters:     R0 == pointer to block of 16 words, for value of R0-R15
;                 R1 == pointer to string to display
;
; On exit:        Most registers corrupted.
;
; Notes:          Use DUMP macro to set up the call.  This will preserve all
;                 registers and set up the save block etc.  This code will
;                 be inserted only if necessary.

		ROUT

		[	hdr_incDump

hdr_regDump	MOV	R8,R14			;Store link
		SWI	XOS_IntOn
		MOV	R9,R0			;Point to reg dump
		MOV	R10,#0			;Register number
		SWI	XOS_WriteS		;Display header
		DCB	6,26,4,12
		DCB	"------------------------------------------"
		DCB	13,10,10
		DCB	"Register dump follows...",0
		ALIGN
		MOV	R0,R1			;Show message from macro
		SWI	XOS_Write0		;Show it
		SWI	XOS_WriteS
		DCB	13,10,10
		DCB	"------------------------------------------"
		DCB	13,10,10,0
		ALIGN
00		ADRL	R0,%f89			;Point to reg name table
		ADD	R0,R0,R10,LSL #2	;Point to correct one
		SWI	XOS_Write0		;Print on the screen
		SWI	XOS_WriteS		;Display next bit
		DCB	" == ",0		;What to display
		ALIGN
		LDR	R0,[R9,R10,LSL #2]	;Get register contents
		CMP	R10,#15			;Is this the PC?
		BICEQ	R0,R0,#&FC000003	;Yes - clear out PSR
		ADRL	R1,%f88			;Buffer
		MOV	R2,#16			;Length of buffer
		SWI	XOS_ConvertHex8		;Convert
		SWI	XOS_Write0		;Show on screen
		SWI	XOS_NewLine		;Start a new line
		CMP	R10,#15			;Have we finished?
		ADDNE	R10,R10,#1		;No: move to next register
		BNE	%b00

		SWI	XOS_NewLine
		SWI	XOS_WriteS		;Display a message
		DCB	"Processor mode: ",0
		ALIGN
		LDR	R7,[R9,R10,LSL #2]	;Get the number again
		AND	R1,R7,#&3		;Get the processor mode
		ADR	R0,%f87			;Point to message table
		ADD	R0,R0,R1,LSL #2		;Get appropriate one
		SWI	XOS_Write0
		SWI	XOS_NewLine
		SWI	XOS_WriteS
		DCB	"FIQ ",0
		ALIGN
		TST	R7,#FIQ_disable
		ADREQ	R0,%f85
		ADRNE	R0,%f86
		SWI	XOS_Write0
		SWI	XOS_WriteS
		DCB	"IRQ ",0
		ALIGN
		TST	R7,#IRQ_disable
		ADREQ	R0,%f85
		ADRNE	R0,%f86
		SWI	XOS_Write0
		SWI	XOS_WriteS
		DCB	"Other flags: ",0
		ALIGN
		TST	R7,#N_flag
		MOVEQ	R0,#'n'
		MOVNE	R0,#'N'
		SWI	XOS_WriteC
		TST	R7,#Z_flag
		MOVEQ	R0,#'z'
		MOVNE	R0,#'Z'
		SWI	XOS_WriteC
		TST	R7,#C_flag
		MOVEQ	R0,#'c'
		MOVNE	R0,#'C'
		SWI	XOS_WriteC
		TST	R7,#V_flag
		MOVEQ	R0,#'v'
		MOVNE	R0,#'V'
		SWI	XOS_WriteC
		SWI	XOS_WriteS
		DCB	13,10,10
		DCB	"Press any key to continue execution...",0
		ALIGN
		SWI	XOS_ReadC
		CMP	R0,#17			;^Q
		SWIEQ	OS_BreakPt
		MOVS	PC,R8

85
		DCB	"enabled",13,10,0
86
		DCB	"disabled",13,10,0

87
		DCB	"USR",0
		DCB	"FIQ",0
		DCB	"IRQ",0
		DCB	"SVC",0

88
		%	16			;Block for translation

89
		DCB	" R0",0
		DCB	" R1",0
		DCB	" R2",0
		DCB	" R3",0
		DCB	" R4",0
		DCB	" R5",0
		DCB	" R6",0
		DCB	" R7",0
		DCB	" R8",0
		DCB	" R9",0
		DCB	"R10",0
		DCB	"R11",0
		DCB	"R12",0
		DCB	"R13",0
		DCB	"R14",0
		DCB	" PC",0
		ALIGN

		]

		END