| 1 | /* |
| 2 | * This file is |
| 3 | * Copyright (C) 1998 Ross Anderson, Eli Biham, Lars Knudsen |
| 4 | * |
| 5 | * For more information see http://www.cl.cam.ac.uk/users/rja14/serpent.html |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2, or (at your option) |
| 10 | * any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software Foundation, |
| 19 | * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 20 | * |
| 21 | */ |
| 22 | |
| 23 | |
| 24 | /* S0: 3 8 15 1 10 6 5 11 14 13 4 2 7 0 9 12 */ |
| 25 | |
| 26 | /* depth = 5,7,4,2, Total gates=18 */ |
| 27 | #define RND00(a,b,c,d,w,x,y,z) \ |
| 28 | { register unsigned long t02, t03, t05, t06, t07, t08, t09, t11, t12, t13, t14, t15, t17, t01;\ |
| 29 | t01 = b ^ c ; \ |
| 30 | t02 = a | d ; \ |
| 31 | t03 = a ^ b ; \ |
| 32 | z = t02 ^ t01; \ |
| 33 | t05 = c | z ; \ |
| 34 | t06 = a ^ d ; \ |
| 35 | t07 = b | c ; \ |
| 36 | t08 = d & t05; \ |
| 37 | t09 = t03 & t07; \ |
| 38 | y = t09 ^ t08; \ |
| 39 | t11 = t09 & y ; \ |
| 40 | t12 = c ^ d ; \ |
| 41 | t13 = t07 ^ t11; \ |
| 42 | t14 = b & t06; \ |
| 43 | t15 = t06 ^ t13; \ |
| 44 | w = ~ t15; \ |
| 45 | t17 = w ^ t14; \ |
| 46 | x = t12 ^ t17; } |
| 47 | |
| 48 | /* InvS0: 13 3 11 0 10 6 5 12 1 14 4 7 15 9 8 2 */ |
| 49 | |
| 50 | /* depth = 8,4,3,6, Total gates=19 */ |
| 51 | #define InvRND00(a,b,c,d,w,x,y,z) \ |
| 52 | { register unsigned long t02, t03, t04, t05, t06, t08, t09, t10, t12, t13, t14, t15, t17, t18, t01;\ |
| 53 | t01 = c ^ d ; \ |
| 54 | t02 = a | b ; \ |
| 55 | t03 = b | c ; \ |
| 56 | t04 = c & t01; \ |
| 57 | t05 = t02 ^ t01; \ |
| 58 | t06 = a | t04; \ |
| 59 | y = ~ t05; \ |
| 60 | t08 = b ^ d ; \ |
| 61 | t09 = t03 & t08; \ |
| 62 | t10 = d | y ; \ |
| 63 | x = t09 ^ t06; \ |
| 64 | t12 = a | t05; \ |
| 65 | t13 = x ^ t12; \ |
| 66 | t14 = t03 ^ t10; \ |
| 67 | t15 = a ^ c ; \ |
| 68 | z = t14 ^ t13; \ |
| 69 | t17 = t05 & t13; \ |
| 70 | t18 = t14 | t17; \ |
| 71 | w = t15 ^ t18; } |
| 72 | |
| 73 | /* S1: 15 12 2 7 9 0 5 10 1 11 14 8 6 13 3 4 */ |
| 74 | |
| 75 | /* depth = 10,7,3,5, Total gates=18 */ |
| 76 | #define RND01(a,b,c,d,w,x,y,z) \ |
| 77 | { register unsigned long t02, t03, t04, t05, t06, t07, t08, t10, t11, t12, t13, t16, t17, t01;\ |
| 78 | t01 = a | d ; \ |
| 79 | t02 = c ^ d ; \ |
| 80 | t03 = ~ b ; \ |
| 81 | t04 = a ^ c ; \ |
| 82 | t05 = a | t03; \ |
| 83 | t06 = d & t04; \ |
| 84 | t07 = t01 & t02; \ |
| 85 | t08 = b | t06; \ |
| 86 | y = t02 ^ t05; \ |
| 87 | t10 = t07 ^ t08; \ |
| 88 | t11 = t01 ^ t10; \ |
| 89 | t12 = y ^ t11; \ |
| 90 | t13 = b & d ; \ |
| 91 | z = ~ t10; \ |
| 92 | x = t13 ^ t12; \ |
| 93 | t16 = t10 | x ; \ |
| 94 | t17 = t05 & t16; \ |
| 95 | w = c ^ t17; } |
| 96 | |
| 97 | /* InvS1: 5 8 2 14 15 6 12 3 11 4 7 9 1 13 10 0 */ |
| 98 | |
| 99 | /* depth = 7,4,5,3, Total gates=18 */ |
| 100 | #define InvRND01(a,b,c,d,w,x,y,z) \ |
| 101 | { register unsigned long t02, t03, t04, t05, t06, t07, t08, t09, t10, t11, t14, t15, t17, t01;\ |
| 102 | t01 = a ^ b ; \ |
| 103 | t02 = b | d ; \ |
| 104 | t03 = a & c ; \ |
| 105 | t04 = c ^ t02; \ |
| 106 | t05 = a | t04; \ |
| 107 | t06 = t01 & t05; \ |
| 108 | t07 = d | t03; \ |
| 109 | t08 = b ^ t06; \ |
| 110 | t09 = t07 ^ t06; \ |
| 111 | t10 = t04 | t03; \ |
| 112 | t11 = d & t08; \ |
| 113 | y = ~ t09; \ |
| 114 | x = t10 ^ t11; \ |
| 115 | t14 = a | y ; \ |
| 116 | t15 = t06 ^ x ; \ |
| 117 | z = t01 ^ t04; \ |
| 118 | t17 = c ^ t15; \ |
| 119 | w = t14 ^ t17; } |
| 120 | |
| 121 | /* S2: 8 6 7 9 3 12 10 15 13 1 14 4 0 11 5 2 */ |
| 122 | |
| 123 | /* depth = 3,8,11,7, Total gates=16 */ |
| 124 | #define RND02(a,b,c,d,w,x,y,z) \ |
| 125 | { register unsigned long t02, t03, t05, t06, t07, t08, t09, t10, t12, t13, t14, t01;\ |
| 126 | t01 = a | c ; \ |
| 127 | t02 = a ^ b ; \ |
| 128 | t03 = d ^ t01; \ |
| 129 | w = t02 ^ t03; \ |
| 130 | t05 = c ^ w ; \ |
| 131 | t06 = b ^ t05; \ |
| 132 | t07 = b | t05; \ |
| 133 | t08 = t01 & t06; \ |
| 134 | t09 = t03 ^ t07; \ |
| 135 | t10 = t02 | t09; \ |
| 136 | x = t10 ^ t08; \ |
| 137 | t12 = a | d ; \ |
| 138 | t13 = t09 ^ x ; \ |
| 139 | t14 = b ^ t13; \ |
| 140 | z = ~ t09; \ |
| 141 | y = t12 ^ t14; } |
| 142 | |
| 143 | /* InvS2: 12 9 15 4 11 14 1 2 0 3 6 13 5 8 10 7 */ |
| 144 | |
| 145 | /* depth = 3,6,8,3, Total gates=18 */ |
| 146 | #define InvRND02(a,b,c,d,w,x,y,z) \ |
| 147 | { register unsigned long t02, t03, t04, t06, t07, t08, t09, t10, t11, t12, t15, t16, t17, t01;\ |
| 148 | t01 = a ^ d ; \ |
| 149 | t02 = c ^ d ; \ |
| 150 | t03 = a & c ; \ |
| 151 | t04 = b | t02; \ |
| 152 | w = t01 ^ t04; \ |
| 153 | t06 = a | c ; \ |
| 154 | t07 = d | w ; \ |
| 155 | t08 = ~ d ; \ |
| 156 | t09 = b & t06; \ |
| 157 | t10 = t08 | t03; \ |
| 158 | t11 = b & t07; \ |
| 159 | t12 = t06 & t02; \ |
| 160 | z = t09 ^ t10; \ |
| 161 | x = t12 ^ t11; \ |
| 162 | t15 = c & z ; \ |
| 163 | t16 = w ^ x ; \ |
| 164 | t17 = t10 ^ t15; \ |
| 165 | y = t16 ^ t17; } |
| 166 | |
| 167 | /* S3: 0 15 11 8 12 9 6 3 13 1 2 4 10 7 5 14 */ |
| 168 | |
| 169 | /* depth = 8,3,5,5, Total gates=18 */ |
| 170 | #define RND03(a,b,c,d,w,x,y,z) \ |
| 171 | { register unsigned long t02, t03, t04, t05, t06, t07, t08, t09, t10, t11, t13, t14, t15, t01;\ |
| 172 | t01 = a ^ c ; \ |
| 173 | t02 = a | d ; \ |
| 174 | t03 = a & d ; \ |
| 175 | t04 = t01 & t02; \ |
| 176 | t05 = b | t03; \ |
| 177 | t06 = a & b ; \ |
| 178 | t07 = d ^ t04; \ |
| 179 | t08 = c | t06; \ |
| 180 | t09 = b ^ t07; \ |
| 181 | t10 = d & t05; \ |
| 182 | t11 = t02 ^ t10; \ |
| 183 | z = t08 ^ t09; \ |
| 184 | t13 = d | z ; \ |
| 185 | t14 = a | t07; \ |
| 186 | t15 = b & t13; \ |
| 187 | y = t08 ^ t11; \ |
| 188 | w = t14 ^ t15; \ |
| 189 | x = t05 ^ t04; } |
| 190 | |
| 191 | /* InvS3: 0 9 10 7 11 14 6 13 3 5 12 2 4 8 15 1 */ |
| 192 | |
| 193 | /* depth = 3,6,4,4, Total gates=17 */ |
| 194 | #define InvRND03(a,b,c,d,w,x,y,z) \ |
| 195 | { register unsigned long t02, t03, t04, t05, t06, t07, t09, t11, t12, t13, t14, t16, t01;\ |
| 196 | t01 = c | d ; \ |
| 197 | t02 = a | d ; \ |
| 198 | t03 = c ^ t02; \ |
| 199 | t04 = b ^ t02; \ |
| 200 | t05 = a ^ d ; \ |
| 201 | t06 = t04 & t03; \ |
| 202 | t07 = b & t01; \ |
| 203 | y = t05 ^ t06; \ |
| 204 | t09 = a ^ t03; \ |
| 205 | w = t07 ^ t03; \ |
| 206 | t11 = w | t05; \ |
| 207 | t12 = t09 & t11; \ |
| 208 | t13 = a & y ; \ |
| 209 | t14 = t01 ^ t05; \ |
| 210 | x = b ^ t12; \ |
| 211 | t16 = b | t13; \ |
| 212 | z = t14 ^ t16; } |
| 213 | |
| 214 | /* S4: 1 15 8 3 12 0 11 6 2 5 4 10 9 14 7 13 */ |
| 215 | |
| 216 | /* depth = 6,7,5,3, Total gates=19 */ |
| 217 | #define RND04(a,b,c,d,w,x,y,z) \ |
| 218 | { register unsigned long t02, t03, t04, t05, t06, t08, t09, t10, t11, t12, t13, t14, t15, t16, t01;\ |
| 219 | t01 = a | b ; \ |
| 220 | t02 = b | c ; \ |
| 221 | t03 = a ^ t02; \ |
| 222 | t04 = b ^ d ; \ |
| 223 | t05 = d | t03; \ |
| 224 | t06 = d & t01; \ |
| 225 | z = t03 ^ t06; \ |
| 226 | t08 = z & t04; \ |
| 227 | t09 = t04 & t05; \ |
| 228 | t10 = c ^ t06; \ |
| 229 | t11 = b & c ; \ |
| 230 | t12 = t04 ^ t08; \ |
| 231 | t13 = t11 | t03; \ |
| 232 | t14 = t10 ^ t09; \ |
| 233 | t15 = a & t05; \ |
| 234 | t16 = t11 | t12; \ |
| 235 | y = t13 ^ t08; \ |
| 236 | x = t15 ^ t16; \ |
| 237 | w = ~ t14; } |
| 238 | |
| 239 | /* InvS4: 5 0 8 3 10 9 7 14 2 12 11 6 4 15 13 1 */ |
| 240 | |
| 241 | /* depth = 6,4,7,3, Total gates=17 */ |
| 242 | #define InvRND04(a,b,c,d,w,x,y,z) \ |
| 243 | { register unsigned long t02, t03, t04, t05, t06, t07, t09, t10, t11, t12, t13, t15, t01;\ |
| 244 | t01 = b | d ; \ |
| 245 | t02 = c | d ; \ |
| 246 | t03 = a & t01; \ |
| 247 | t04 = b ^ t02; \ |
| 248 | t05 = c ^ d ; \ |
| 249 | t06 = ~ t03; \ |
| 250 | t07 = a & t04; \ |
| 251 | x = t05 ^ t07; \ |
| 252 | t09 = x | t06; \ |
| 253 | t10 = a ^ t07; \ |
| 254 | t11 = t01 ^ t09; \ |
| 255 | t12 = d ^ t04; \ |
| 256 | t13 = c | t10; \ |
| 257 | z = t03 ^ t12; \ |
| 258 | t15 = a ^ t04; \ |
| 259 | y = t11 ^ t13; \ |
| 260 | w = t15 ^ t09; } |
| 261 | |
| 262 | /* S5: 15 5 2 11 4 10 9 12 0 3 14 8 13 6 7 1 */ |
| 263 | |
| 264 | /* depth = 4,6,8,6, Total gates=17 */ |
| 265 | #define RND05(a,b,c,d,w,x,y,z) \ |
| 266 | { register unsigned long t02, t03, t04, t05, t07, t08, t09, t10, t11, t12, t13, t14, t01;\ |
| 267 | t01 = b ^ d ; \ |
| 268 | t02 = b | d ; \ |
| 269 | t03 = a & t01; \ |
| 270 | t04 = c ^ t02; \ |
| 271 | t05 = t03 ^ t04; \ |
| 272 | w = ~ t05; \ |
| 273 | t07 = a ^ t01; \ |
| 274 | t08 = d | w ; \ |
| 275 | t09 = b | t05; \ |
| 276 | t10 = d ^ t08; \ |
| 277 | t11 = b | t07; \ |
| 278 | t12 = t03 | w ; \ |
| 279 | t13 = t07 | t10; \ |
| 280 | t14 = t01 ^ t11; \ |
| 281 | y = t09 ^ t13; \ |
| 282 | x = t07 ^ t08; \ |
| 283 | z = t12 ^ t14; } |
| 284 | |
| 285 | /* InvS5: 8 15 2 9 4 1 13 14 11 6 5 3 7 12 10 0 */ |
| 286 | |
| 287 | /* depth = 4,6,9,7, Total gates=17 */ |
| 288 | #define InvRND05(a,b,c,d,w,x,y,z) \ |
| 289 | { register unsigned long t02, t03, t04, t05, t07, t08, t09, t10, t12, t13, t15, t16, t01;\ |
| 290 | t01 = a & d ; \ |
| 291 | t02 = c ^ t01; \ |
| 292 | t03 = a ^ d ; \ |
| 293 | t04 = b & t02; \ |
| 294 | t05 = a & c ; \ |
| 295 | w = t03 ^ t04; \ |
| 296 | t07 = a & w ; \ |
| 297 | t08 = t01 ^ w ; \ |
| 298 | t09 = b | t05; \ |
| 299 | t10 = ~ b ; \ |
| 300 | x = t08 ^ t09; \ |
| 301 | t12 = t10 | t07; \ |
| 302 | t13 = w | x ; \ |
| 303 | z = t02 ^ t12; \ |
| 304 | t15 = t02 ^ t13; \ |
| 305 | t16 = b ^ d ; \ |
| 306 | y = t16 ^ t15; } |
| 307 | |
| 308 | /* S6: 7 2 12 5 8 4 6 11 14 9 1 15 13 3 10 0 */ |
| 309 | |
| 310 | /* depth = 8,3,6,3, Total gates=19 */ |
| 311 | #define RND06(a,b,c,d,w,x,y,z) \ |
| 312 | { register unsigned long t02, t03, t04, t05, t07, t08, t09, t10, t11, t12, t13, t15, t17, t18, t01;\ |
| 313 | t01 = a & d ; \ |
| 314 | t02 = b ^ c ; \ |
| 315 | t03 = a ^ d ; \ |
| 316 | t04 = t01 ^ t02; \ |
| 317 | t05 = b | c ; \ |
| 318 | x = ~ t04; \ |
| 319 | t07 = t03 & t05; \ |
| 320 | t08 = b & x ; \ |
| 321 | t09 = a | c ; \ |
| 322 | t10 = t07 ^ t08; \ |
| 323 | t11 = b | d ; \ |
| 324 | t12 = c ^ t11; \ |
| 325 | t13 = t09 ^ t10; \ |
| 326 | y = ~ t13; \ |
| 327 | t15 = x & t03; \ |
| 328 | z = t12 ^ t07; \ |
| 329 | t17 = a ^ b ; \ |
| 330 | t18 = y ^ t15; \ |
| 331 | w = t17 ^ t18; } |
| 332 | |
| 333 | /* InvS6: 15 10 1 13 5 3 6 0 4 9 14 7 2 12 8 11 */ |
| 334 | |
| 335 | /* depth = 5,3,8,6, Total gates=19 */ |
| 336 | #define InvRND06(a,b,c,d,w,x,y,z) \ |
| 337 | { register unsigned long t02, t03, t04, t05, t06, t07, t08, t09, t12, t13, t14, t15, t16, t17, t01;\ |
| 338 | t01 = a ^ c ; \ |
| 339 | t02 = ~ c ; \ |
| 340 | t03 = b & t01; \ |
| 341 | t04 = b | t02; \ |
| 342 | t05 = d | t03; \ |
| 343 | t06 = b ^ d ; \ |
| 344 | t07 = a & t04; \ |
| 345 | t08 = a | t02; \ |
| 346 | t09 = t07 ^ t05; \ |
| 347 | x = t06 ^ t08; \ |
| 348 | w = ~ t09; \ |
| 349 | t12 = b & w ; \ |
| 350 | t13 = t01 & t05; \ |
| 351 | t14 = t01 ^ t12; \ |
| 352 | t15 = t07 ^ t13; \ |
| 353 | t16 = d | t02; \ |
| 354 | t17 = a ^ x ; \ |
| 355 | z = t17 ^ t15; \ |
| 356 | y = t16 ^ t14; } |
| 357 | |
| 358 | /* S7: 1 13 15 0 14 8 2 11 7 4 12 10 9 3 5 6 */ |
| 359 | |
| 360 | /* depth = 10,7,10,4, Total gates=19 */ |
| 361 | #define RND07(a,b,c,d,w,x,y,z) \ |
| 362 | { register unsigned long t02, t03, t04, t05, t06, t08, t09, t10, t11, t13, t14, t15, t16, t17, t01;\ |
| 363 | t01 = a & c ; \ |
| 364 | t02 = ~ d ; \ |
| 365 | t03 = a & t02; \ |
| 366 | t04 = b | t01; \ |
| 367 | t05 = a & b ; \ |
| 368 | t06 = c ^ t04; \ |
| 369 | z = t03 ^ t06; \ |
| 370 | t08 = c | z ; \ |
| 371 | t09 = d | t05; \ |
| 372 | t10 = a ^ t08; \ |
| 373 | t11 = t04 & z ; \ |
| 374 | x = t09 ^ t10; \ |
| 375 | t13 = b ^ x ; \ |
| 376 | t14 = t01 ^ x ; \ |
| 377 | t15 = c ^ t05; \ |
| 378 | t16 = t11 | t13; \ |
| 379 | t17 = t02 | t14; \ |
| 380 | w = t15 ^ t17; \ |
| 381 | y = a ^ t16; } |
| 382 | |
| 383 | /* InvS7: 3 0 6 13 9 14 15 8 5 12 11 7 10 1 4 2 */ |
| 384 | |
| 385 | /* depth = 9,7,3,3, Total gates=18 */ |
| 386 | #define InvRND07(a,b,c,d,w,x,y,z) \ |
| 387 | { register unsigned long t02, t03, t04, t06, t07, t08, t09, t10, t11, t13, t14, t15, t16, t01;\ |
| 388 | t01 = a & b ; \ |
| 389 | t02 = a | b ; \ |
| 390 | t03 = c | t01; \ |
| 391 | t04 = d & t02; \ |
| 392 | z = t03 ^ t04; \ |
| 393 | t06 = b ^ t04; \ |
| 394 | t07 = d ^ z ; \ |
| 395 | t08 = ~ t07; \ |
| 396 | t09 = t06 | t08; \ |
| 397 | t10 = b ^ d ; \ |
| 398 | t11 = a | d ; \ |
| 399 | x = a ^ t09; \ |
| 400 | t13 = c ^ t06; \ |
| 401 | t14 = c & t11; \ |
| 402 | t15 = d | x ; \ |
| 403 | t16 = t01 | t10; \ |
| 404 | w = t13 ^ t15; \ |
| 405 | y = t14 ^ t16; } |
| 406 | |
| 407 | #define RND08(a,b,c,d,e,f,g,h) RND00(a,b,c,d,e,f,g,h) |
| 408 | #define RND09(a,b,c,d,e,f,g,h) RND01(a,b,c,d,e,f,g,h) |
| 409 | #define RND10(a,b,c,d,e,f,g,h) RND02(a,b,c,d,e,f,g,h) |
| 410 | #define RND11(a,b,c,d,e,f,g,h) RND03(a,b,c,d,e,f,g,h) |
| 411 | #define RND12(a,b,c,d,e,f,g,h) RND04(a,b,c,d,e,f,g,h) |
| 412 | #define RND13(a,b,c,d,e,f,g,h) RND05(a,b,c,d,e,f,g,h) |
| 413 | #define RND14(a,b,c,d,e,f,g,h) RND06(a,b,c,d,e,f,g,h) |
| 414 | #define RND15(a,b,c,d,e,f,g,h) RND07(a,b,c,d,e,f,g,h) |
| 415 | #define RND16(a,b,c,d,e,f,g,h) RND00(a,b,c,d,e,f,g,h) |
| 416 | #define RND17(a,b,c,d,e,f,g,h) RND01(a,b,c,d,e,f,g,h) |
| 417 | #define RND18(a,b,c,d,e,f,g,h) RND02(a,b,c,d,e,f,g,h) |
| 418 | #define RND19(a,b,c,d,e,f,g,h) RND03(a,b,c,d,e,f,g,h) |
| 419 | #define RND20(a,b,c,d,e,f,g,h) RND04(a,b,c,d,e,f,g,h) |
| 420 | #define RND21(a,b,c,d,e,f,g,h) RND05(a,b,c,d,e,f,g,h) |
| 421 | #define RND22(a,b,c,d,e,f,g,h) RND06(a,b,c,d,e,f,g,h) |
| 422 | #define RND23(a,b,c,d,e,f,g,h) RND07(a,b,c,d,e,f,g,h) |
| 423 | #define RND24(a,b,c,d,e,f,g,h) RND00(a,b,c,d,e,f,g,h) |
| 424 | #define RND25(a,b,c,d,e,f,g,h) RND01(a,b,c,d,e,f,g,h) |
| 425 | #define RND26(a,b,c,d,e,f,g,h) RND02(a,b,c,d,e,f,g,h) |
| 426 | #define RND27(a,b,c,d,e,f,g,h) RND03(a,b,c,d,e,f,g,h) |
| 427 | #define RND28(a,b,c,d,e,f,g,h) RND04(a,b,c,d,e,f,g,h) |
| 428 | #define RND29(a,b,c,d,e,f,g,h) RND05(a,b,c,d,e,f,g,h) |
| 429 | #define RND30(a,b,c,d,e,f,g,h) RND06(a,b,c,d,e,f,g,h) |
| 430 | #define RND31(a,b,c,d,e,f,g,h) RND07(a,b,c,d,e,f,g,h) |
| 431 | |
| 432 | #define InvRND08(a,b,c,d,e,f,g,h) InvRND00(a,b,c,d,e,f,g,h) |
| 433 | #define InvRND09(a,b,c,d,e,f,g,h) InvRND01(a,b,c,d,e,f,g,h) |
| 434 | #define InvRND10(a,b,c,d,e,f,g,h) InvRND02(a,b,c,d,e,f,g,h) |
| 435 | #define InvRND11(a,b,c,d,e,f,g,h) InvRND03(a,b,c,d,e,f,g,h) |
| 436 | #define InvRND12(a,b,c,d,e,f,g,h) InvRND04(a,b,c,d,e,f,g,h) |
| 437 | #define InvRND13(a,b,c,d,e,f,g,h) InvRND05(a,b,c,d,e,f,g,h) |
| 438 | #define InvRND14(a,b,c,d,e,f,g,h) InvRND06(a,b,c,d,e,f,g,h) |
| 439 | #define InvRND15(a,b,c,d,e,f,g,h) InvRND07(a,b,c,d,e,f,g,h) |
| 440 | #define InvRND16(a,b,c,d,e,f,g,h) InvRND00(a,b,c,d,e,f,g,h) |
| 441 | #define InvRND17(a,b,c,d,e,f,g,h) InvRND01(a,b,c,d,e,f,g,h) |
| 442 | #define InvRND18(a,b,c,d,e,f,g,h) InvRND02(a,b,c,d,e,f,g,h) |
| 443 | #define InvRND19(a,b,c,d,e,f,g,h) InvRND03(a,b,c,d,e,f,g,h) |
| 444 | #define InvRND20(a,b,c,d,e,f,g,h) InvRND04(a,b,c,d,e,f,g,h) |
| 445 | #define InvRND21(a,b,c,d,e,f,g,h) InvRND05(a,b,c,d,e,f,g,h) |
| 446 | #define InvRND22(a,b,c,d,e,f,g,h) InvRND06(a,b,c,d,e,f,g,h) |
| 447 | #define InvRND23(a,b,c,d,e,f,g,h) InvRND07(a,b,c,d,e,f,g,h) |
| 448 | #define InvRND24(a,b,c,d,e,f,g,h) InvRND00(a,b,c,d,e,f,g,h) |
| 449 | #define InvRND25(a,b,c,d,e,f,g,h) InvRND01(a,b,c,d,e,f,g,h) |
| 450 | #define InvRND26(a,b,c,d,e,f,g,h) InvRND02(a,b,c,d,e,f,g,h) |
| 451 | #define InvRND27(a,b,c,d,e,f,g,h) InvRND03(a,b,c,d,e,f,g,h) |
| 452 | #define InvRND28(a,b,c,d,e,f,g,h) InvRND04(a,b,c,d,e,f,g,h) |
| 453 | #define InvRND29(a,b,c,d,e,f,g,h) InvRND05(a,b,c,d,e,f,g,h) |
| 454 | #define InvRND30(a,b,c,d,e,f,g,h) InvRND06(a,b,c,d,e,f,g,h) |
| 455 | #define InvRND31(a,b,c,d,e,f,g,h) InvRND07(a,b,c,d,e,f,g,h) |
| 456 | |
| 457 | /* Linear transformations and key mixing: */ |
| 458 | |
| 459 | #define ROL(x,n) ((((unsigned long)(x))<<(n))| \ |
| 460 | (((unsigned long)(x))>>(32-(n)))) |
| 461 | #define ROR(x,n) ((((unsigned long)(x))<<(32-(n)))| \ |
| 462 | (((unsigned long)(x))>>(n))) |
| 463 | |
| 464 | #define transform(x0, x1, x2, x3, y0, y1, y2, y3) \ |
| 465 | y0 = ROL(x0, 13); \ |
| 466 | y2 = ROL(x2, 3); \ |
| 467 | y1 = x1 ^ y0 ^ y2; \ |
| 468 | y3 = x3 ^ y2 ^ ((unsigned long)y0)<<3; \ |
| 469 | y1 = ROL(y1, 1); \ |
| 470 | y3 = ROL(y3, 7); \ |
| 471 | y0 = y0 ^ y1 ^ y3; \ |
| 472 | y2 = y2 ^ y3 ^ ((unsigned long)y1<<7); \ |
| 473 | y0 = ROL(y0, 5); \ |
| 474 | y2 = ROL(y2, 22) |
| 475 | |
| 476 | #define inv_transform(x0, x1, x2, x3, y0, y1, y2, y3) \ |
| 477 | y2 = ROR(x2, 22);\ |
| 478 | y0 = ROR(x0, 5); \ |
| 479 | y2 = y2 ^ x3 ^ ((unsigned long)x1<<7); \ |
| 480 | y0 = y0 ^ x1 ^ x3; \ |
| 481 | y3 = ROR(x3, 7); \ |
| 482 | y1 = ROR(x1, 1); \ |
| 483 | y3 = y3 ^ y2 ^ ((unsigned long)y0)<<3; \ |
| 484 | y1 = y1 ^ y0 ^ y2; \ |
| 485 | y2 = ROR(y2, 3); \ |
| 486 | y0 = ROR(y0, 13) |
| 487 | |
| 488 | #define keying(x0, x1, x2, x3, subkey) \ |
| 489 | x0^=subkey[0];x1^=subkey[1]; \ |
| 490 | x2^=subkey[2];x3^=subkey[3] |
| 491 | |
| 492 | /* PHI: Constant used in the key schedule */ |
| 493 | #define PHI 0x9e3779b9L |