From d25653be0dfcf2cccb8edf75227604ba14cf036e Mon Sep 17 00:00:00 2001 From: Mark Wooding Date: Thu, 26 May 2016 09:26:09 +0100 Subject: [PATCH] base/dispatch.[ch]: Detect availability of the x86 `RDRAND' instruction. --- base/dispatch.c | 3 +++ base/dispatch.h | 3 ++- 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/base/dispatch.c b/base/dispatch.c index b2a032e5..51619d50 100644 --- a/base/dispatch.c +++ b/base/dispatch.c @@ -47,6 +47,7 @@ # define CPUID1D_SSE2 (1u << 26) # define CPUID1D_FXSR (1u << 24) # define CPUID1C_AESNI (1u << 25) +# define CPUID1C_RDRAND (1u << 30) struct cpuid { unsigned a, b, c, d; }; @@ -516,6 +517,8 @@ int cpu_feature_p(int feat) CASE_CPUFEAT(X86_AESNI, "x86:aesni", xmm_registers_available_p() && cpuid_features_p(CPUID1D_SSE2, CPUID1C_AESNI)); + CASE_CPUFEAT(X86_RDRAND, "x86:rdrand", + cpuid_features_p(0, CPUID1C_RDRAND)); #endif #ifdef CAPMAP # define FEATP__CASE(feat, tok) \ diff --git a/base/dispatch.h b/base/dispatch.h index 1e463bdc..1983a5a4 100644 --- a/base/dispatch.h +++ b/base/dispatch.h @@ -179,7 +179,8 @@ enum { CPUFEAT_ARM_VFP, /* VFP floating-point (v3 or v4) */ CPUFEAT_ARM_NEON, /* Advanced SIMD (v1 or v2) */ CPUFEAT_ARM_V4, /* VFPv4 and/or SIMD v2 */ - CPUFEAT_ARM_D32 /* 32 double registers, not 16 */ + CPUFEAT_ARM_D32, /* 32 double registers, not 16 */ + CPUFEAT_X86_RDRAND /* Built-in entropy source */ }; extern int cpu_feature_p(int /*feat*/); -- 2.11.0