X-Git-Url: https://git.distorted.org.uk/~mdw/catacomb/blobdiff_plain/cdc153a5b79da5a1c9e06620c4d2ed6095d6ba04..25f3ce6a509ff9e3a354303023cb2028e9f83b95:/base/asm-common.h

diff --git a/base/asm-common.h b/base/asm-common.h
index 10a79a50..44c223da 100644
--- a/base/asm-common.h
+++ b/base/asm-common.h
@@ -453,7 +453,7 @@ name:
 #define WHOLE(reg) _REGFORM(reg, r)
 
 // Stack management and unwinding.
-.macro	setfp	fp, offset=0
+.macro	setfp	fp=R_bp(r), offset=0
   .if \offset == 0
 	mov	\fp, R_sp(r)
 #if __ELF__
@@ -549,117 +549,6 @@ name:
 
 #endif
 
-#if CPUFAM_X86
-
-.macro	_reg.0
-	// Stash GP registers and establish temporary stack frame.
-	pushfd
-	push	eax
-	push	ecx
-	push	edx
-	push	ebp
-	mov	ebp, esp
-	and	esp, ~15
-	sub	esp, 512
-	fxsave	[esp]
-.endm
-
-.macro	_reg.1
-.endm
-
-.macro	_reg.2
-.endm
-
-.macro	_reg.3	fmt
-	// Print FMT and the other established arguments.
-	lea	eax, .L$_reg$msg.\@
-	push	eax
-	call	printf
-	jmp	.L$_reg$cont.\@
-.L$_reg$msg.\@:
-	.ascii	";; \fmt\n\0"
-.L$_reg$cont.\@:
-	mov	eax, ebp
-	and	eax, ~15
-	sub	eax, 512
-	fxrstor	[eax]
-	mov	esp, ebp
-	pop	ebp
-	pop	edx
-	pop	ecx
-	pop	eax
-	popfd
-.endm
-
-.macro	msg	msg
-	_reg.0
-	_reg.1
-	_reg.2
-	_reg.3	"\msg"
-.endm
-
-.macro	reg	r, msg
-	_reg.0
-  .ifeqs "\r", "esp"
-	lea	eax, [ebp + 20]
-	push	eax
-  .else
-    .ifeqs "\r", "ebp"
-	push	[ebp]
-    .else
-	push	\r
-    .endif
-  .endif
-	_reg.1
-	_reg.2
-	_reg.3	"\msg: \r = %08x"
-.endm
-
-.macro	xmmreg	r, msg
-	_reg.0
-	_reg.1
-	_reg.2
-	movdqu	xmm0, \r
-	pshufd	xmm0, xmm0, 0x1b
-	sub	esp, 16
-	movdqa	[esp], xmm0
-	_reg.3	"\msg: \r = %08x %08x %08x %08x"
-.endm
-
-.macro	mmreg	r, msg
-	_reg.0
-	_reg.1
-	_reg.2
-	pshufw	\r, \r, 0x4e
-	sub	esp, 8
-	movq	[esp], \r
-	_reg.3	"\msg: \r = %08x %08x"
-.endm
-
-.macro	freg	i, msg
-	_reg.0
-	_reg.1
-	_reg.2
-	finit
-	fldt	[esp + 32 + 16*\i]
-	sub	esp, 12
-	fstpt	[esp]
-	_reg.3	"\msg: st(\i) = %.20Lg"
-.endm
-
-.macro	fxreg	i, msg
-	_reg.0
-	_reg.1
-	_reg.2
-	finit
-	fldt	[esp + 32 + 16*\i]
-	sub	esp, 12
-	fstpt	[esp]
-	_reg.3	"\msg: st(\i) = %La"
-.endm
-
-#endif
-
 ///--------------------------------------------------------------------------
 /// ARM-specific hacking.
 
@@ -723,12 +612,12 @@ name:
 #if WANT_PIC
 	ldr\cond \reg, .L$_leaextq$\@
 .L$_leaextq_pc$\@:
-	.if	.L$_pcoff == 8
+  .if .L$_pcoff == 8
 	ldr\cond \reg, [pc, \reg]
-	.else
+  .else
 	add\cond \reg, pc
 	ldr\cond \reg, [\reg]
-	.endif
+  .endif
   _LIT
 	.balign	4
 .L$_leaextq$\@:
@@ -739,6 +628,29 @@ name:
 #endif
 .endm
 
+.macro	vzero	vz=q15
+	// Set VZ (default q15) to zero.
+	vmov.u32 \vz, #0
+.endm
+
+.macro	vshl128	vd, vn, nbit, vz=q15
+	// Set VD to VN shifted left by NBIT.  Assume VZ (default q15) is
+	// all-bits-zero.  NBIT must be a multiple of 8.
+  .if \nbit&3 != 0
+	.error	"shift quantity must be whole number of bytes"
+  .endif
+	vext.8	\vd, \vz, \vn, #16 - (\nbit >> 3)
+.endm
+
+.macro	vshr128	vd, vn, nbit, vz=q15
+	// Set VD to VN shifted right by NBIT.  Assume VZ (default q15) is
+	// all-bits-zero.  NBIT must be a multiple of 8.
+  .if \nbit&3 != 0
+	.error	"shift quantity must be whole number of bytes"
+  .endif
+	vext.8	\vd, \vn, \vz, #\nbit >> 3
+.endm
+
 // Apply decoration decor to register name reg.
 #define _REGFORM(reg, decor) _GLUE(_REGFORM_, reg)(decor)
 
@@ -989,7 +901,7 @@ name:
 #define QQ(qlo, qhi) D0(qlo)-D1(qhi)
 
 // Stack management and unwinding.
-.macro	setfp	fp, offset=0
+.macro	setfp	fp=r11, offset=0
   .if \offset == 0
 	mov	\fp, sp
 	  .setfp \fp, sp
@@ -1022,12 +934,12 @@ name:
 .endm
 
 .macro	pushreg	rr:vararg
-	stmfd	sp!, {\rr}
+	push	{\rr}
 	  .save {\rr}
 .endm
 
 .macro	popreg	rr:vararg
-	ldmfd	sp!, {\rr}
+	pop	{\rr}
 .endm
 
 .macro	pushvfp rr:vararg
@@ -1073,8 +985,31 @@ name:
 #endif
 .endm
 
+.macro	vzero	vz=v31
+	// Set VZ (default v31) to zero.
+	dup	\vz\().4s, wzr
+.endm
+
+.macro	vshl128	vd, vn, nbit, vz=v31
+	// Set VD to VN shifted left by NBIT.  Assume VZ (default v31) is
+	// all-bits-zero.  NBIT must be a multiple of 8.
+  .if \nbit&3 != 0
+	.error	"shift quantity must be whole number of bytes"
+  .endif
+	ext	\vd\().16b, \vz\().16b, \vn\().16b, #16 - (\nbit >> 3)
+.endm
+
+.macro	vshr128	vd, vn, nbit, vz=v31
+	// Set VD to VN shifted right by NBIT.  Assume VZ (default v31) is
+	// all-bits-zero.  NBIT must be a multiple of 8.
+  .if \nbit&3 != 0
+	.error	"shift quantity must be whole number of bytes"
+  .endif
+	ext	\vd\().16b, \vn\().16b, \vz\().16b, #\nbit >> 3
+.endm
+
 // Stack management and unwinding.
-.macro	setfp	fp, offset=0
+.macro	setfp	fp=x29, offset=0
   // If you're just going through the motions with a fixed-size stack frame,
   // then you want to say `add x29, sp, #OFFSET' directly, which will avoid
   // pointlessly restoring sp later.
@@ -1113,8 +1048,8 @@ name:
 	  .cfi_adjust_cfa_offset -\n
 .endm
 
-.macro	pushreg	x, y=
-  .ifeqs "\y", ""
+.macro	pushreg	x, y=nil
+  .ifeqs "\y", "nil"
 	str	\x, [sp, #-16]!
 	  .cfi_adjust_cfa_offset +16
 	  .cfi_rel_offset \x, 0
@@ -1126,8 +1061,8 @@ name:
   .endif
 .endm
 
-.macro	popreg	x, y=
-  .ifeqs "\y", ""
+.macro	popreg	x, y=nil
+  .ifeqs "\y", "nil"
 	ldr	\x, [sp], #16
 	  .cfi_restore \x
 	  .cfi_adjust_cfa_offset -16
@@ -1139,9 +1074,9 @@ name:
   .endif
 .endm
 
-.macro	savereg	x, y, z=
-  .ifeqs "\z", ""
-	str	\x, [sp, #\y]
+.macro	savereg	x, y, z=nil
+  .ifeqs "\z", "nil"
+	str	\x, [sp, \y]
 	  .cfi_rel_offset \x, \y
   .else
 	stp	\x, \y, [sp, #\z]
@@ -1150,9 +1085,9 @@ name:
   .endif
 .endm
 
-.macro	rstrreg	x, y, z=
-  .ifeqs "\z", ""
-	ldr	\x, [sp, #\y]
+.macro	rstrreg	x, y, z=nil
+  .ifeqs "\z", "nil"
+	ldr	\x, [sp, \y]
 	  .cfi_restore \x
   .else
 	ldp	\x, \y, [sp, #\z]
@@ -1181,7 +1116,11 @@ name:
 #endif
 
 #ifndef F
-#  define F(name) name
+#  ifdef SYM_USCORE
+#    define F(name) _##name
+#  else
+#    define F(name) name
+#  endif
 #endif
 
 #ifndef TYPE_FUNC