/// MA 02111-1307, USA.
///--------------------------------------------------------------------------
-/// External definitions.
+/// Preliminaries.
#include "config.h"
#include "asm-common.h"
-///--------------------------------------------------------------------------
-/// Main.code.
-
.arch armv8-a
+
.text
+///--------------------------------------------------------------------------
+/// Main code.
+
FUNC(salsa20_core_arm64)
// Arguments are in registers.
// b ^= (a + d) <<< 7
add v16.4s, v0.4s, v3.4s
shl v17.4s, v16.4s, #7
- ushr v16.4s, v16.4s, #25
- orr v16.16b, v16.16b, v17.16b
- eor v5.16b, v1.16b, v16.16b
+ sri v17.4s, v16.4s, #25
+ eor v5.16b, v1.16b, v17.16b
// c ^= (b + a) <<< 9
add v16.4s, v5.4s, v0.4s
shl v17.4s, v16.4s, #9
- ushr v16.4s, v16.4s, #23
- orr v16.16b, v16.16b, v17.16b
- eor v6.16b, v2.16b, v16.16b
+ sri v17.4s, v16.4s, #23
+ eor v6.16b, v2.16b, v17.16b
// d ^= (c + b) <<< 13
add v16.4s, v6.4s, v5.4s
ext v5.16b, v5.16b, v5.16b, #12
shl v17.4s, v16.4s, #13
- ushr v16.4s, v16.4s, #19
- orr v16.16b, v16.16b, v17.16b
- eor v7.16b, v3.16b, v16.16b
+ sri v17.4s, v16.4s, #19
+ eor v7.16b, v3.16b, v17.16b
// a ^= (d + c) <<< 18
add v16.4s, v7.4s, v6.4s
ext v6.16b, v6.16b, v6.16b, #8
ext v7.16b, v7.16b, v7.16b, #4
shl v17.4s, v16.4s, #18
- ushr v16.4s, v16.4s, #14
- orr v16.16b, v16.16b, v17.16b
- eor v4.16b, v0.16b, v16.16b
+ sri v17.4s, v16.4s, #14
+ eor v4.16b, v0.16b, v17.16b
0:
// The transpose conveniently only involves reordering elements of
// b ^= (a + d) <<< 7
add v16.4s, v4.4s, v5.4s
shl v17.4s, v16.4s, #7
- ushr v16.4s, v16.4s, #25
- orr v16.16b, v16.16b, v17.16b
- eor v7.16b, v7.16b, v16.16b
+ sri v17.4s, v16.4s, #25
+ eor v7.16b, v7.16b, v17.16b
// c ^= (b + a) <<< 9
add v16.4s, v7.4s, v4.4s
shl v17.4s, v16.4s, #9
- ushr v16.4s, v16.4s, #23
- orr v16.16b, v16.16b, v17.16b
- eor v6.16b, v6.16b, v16.16b
+ sri v17.4s, v16.4s, #23
+ eor v6.16b, v6.16b, v17.16b
// d ^= (c + b) <<< 13
add v16.4s, v6.4s, v7.4s
ext v7.16b, v7.16b, v7.16b, #12
shl v17.4s, v16.4s, #13
- ushr v16.4s, v16.4s, #19
- orr v16.16b, v16.16b, v17.16b
- eor v5.16b, v5.16b, v16.16b
+ sri v17.4s, v16.4s, #19
+ eor v5.16b, v5.16b, v17.16b
// a ^= (d + c) <<< 18
add v16.4s, v5.4s, v6.4s
ext v6.16b, v6.16b, v6.16b, #8
ext v5.16b, v5.16b, v5.16b, #4
shl v17.4s, v16.4s, #18
- ushr v16.4s, v16.4s, #14
- orr v16.16b, v16.16b, v17.16b
- eor v4.16b, v4.16b, v16.16b
+ sri v17.4s, v16.4s, #14
+ eor v4.16b, v4.16b, v17.16b
// We had to undo the transpose ready for the next loop. Again, push
// back the reorderings to reduce latency. Decrement the loop
// b ^= (a + d) <<< 7
add v16.4s, v4.4s, v7.4s
shl v17.4s, v16.4s, #7
- ushr v16.4s, v16.4s, #25
- orr v16.16b, v16.16b, v17.16b
- eor v5.16b, v5.16b, v16.16b
+ sri v17.4s, v16.4s, #25
+ eor v5.16b, v5.16b, v17.16b
// c ^= (b + a) <<< 9
add v16.4s, v5.4s, v4.4s
shl v17.4s, v16.4s, #9
- ushr v16.4s, v16.4s, #23
- orr v16.16b, v16.16b, v17.16b
- eor v6.16b, v6.16b, v16.16b
+ sri v17.4s, v16.4s, #23
+ eor v6.16b, v6.16b, v17.16b
// d ^= (c + b) <<< 13
add v16.4s, v6.4s, v5.4s
ext v5.16b, v5.16b, v5.16b, #12
shl v17.4s, v16.4s, #13
- ushr v16.4s, v16.4s, #19
- orr v16.16b, v16.16b, v17.16b
- eor v7.16b, v7.16b, v16.16b
+ sri v17.4s, v16.4s, #19
+ eor v7.16b, v7.16b, v17.16b
// a ^= (d + c) <<< 18
add v16.4s, v7.4s, v6.4s
ext v6.16b, v6.16b, v6.16b, #8
ext v7.16b, v7.16b, v7.16b, #4
shl v17.4s, v16.4s, #18
- ushr v16.4s, v16.4s, #14
- orr v16.16b, v16.16b, v17.16b
- eor v4.16b, v4.16b, v16.16b
+ sri v17.4s, v16.4s, #14
+ eor v4.16b, v4.16b, v17.16b
b 0b
// Almost there. Firstly the feedfoward addition. Also, establish
// constants which will be useful later.
9: add v0.4s, v0.4s, v4.4s // 0, 5, 10, 15
- movi v16.2d, #0xffffffff // = (-1, 0, -1, 0)
- movi d17, #-1 // = (-1, -1, 0, 0)
+ movi v16.2d, #0xffffffff // = (0, -1; 0, -1)
+ movi d17, #-1 // = (0, 0; -1, -1)
add v1.4s, v1.4s, v5.4s // 4, 9, 14, 3
add v2.4s, v2.4s, v6.4s // 8, 13, 2, 7
add v3.4s, v3.4s, v7.4s // 12, 1, 6, 11
~mdw / catacomb / blobdiff