Support Intel's AES Native Instructions where available on x86 hardware.

[catacomb] / base / dispatch.c

diff --git a/base/dispatch.c b/base/dispatch.c
index 87d41b3..fe3dcfb 100644 (file)
--- a/base/dispatch.c
+++ b/base/dispatch.c
@@ -44,6 +44,7 @@
 #define EFLAGS_ID (1u << 21)
 #define CPUID1D_SSE2 (1u << 26)
 #define CPUID1D_FXSR (1u << 24)
+#define CPUID1C_AESNI (1u << 25)
 
 struct cpuid { unsigned a, b, c, d; };
 
@@ -196,6 +197,11 @@ int cpu_feature_p(int feat)
       return (xmm_registers_available_p() &&
              cpuid_features_p(CPUID1D_SSE2, 0));
     }
+    case CPUFEAT_X86_AESNI: {
+      check_env("x86:aesni");
+      return (xmm_registers_available_p() &&
+             cpuid_features_p(CPUID1D_SSE2, CPUID1C_AESNI));
+    }
 #endif
     default:
       return (0);