// R_r(decor) applies decoration decor to register r, which is an internal
// register name. The internal register names are: `ip', `a', `b', `c', `d',
// `si', `di', `bp', `sp', `r8'--`r15'.
+#define R_nil(decor) nil
#define R_ip(decor) _DECOR(ip, decor, ip)
#define R_a(decor) _DECOR(abcd, decor, a)
#define R_b(decor) _DECOR(abcd, decor, b)
// assembler-level register name, in place of any decoration that register
// name has already.
+#define _REGFORM_nil(decor) R_nil(decor)
+
#define _REGFORM_ip(decor) R_ip(decor)
#define _REGFORM_eip(decor) R_ip(decor)
#endif
#define WHOLE(reg) _REGFORM(reg, r)
+// Macros for some common registers.
+#define AX R_a(r)
+#define BX R_b(r)
+#define CX R_c(r)
+#define DX R_d(r)
+#define SI R_si(r)
+#define DI R_di(r)
+#define BP R_bp(r)
+#define SP R_sp(r)
+
// Stack management and unwinding.
-.macro setfp fp, offset = 0
+.macro setfp fp=BP, offset=0
.if \offset == 0
- mov \fp, R_sp(r)
+ mov \fp, SP
#if __ELF__
.cfi_def_cfa_register \fp
#endif
.seh_setframe \fp, 0
#endif
.else
- lea \fp, [R_sp(r) + \offset]
+ lea \fp, [SP + \offset]
#if __ELF__
.cfi_def_cfa_register \fp
.cfi_adjust_cfa_offset -\offset
.macro dropfp; _dropfp \fp, \offset; .endm
.endm
-.macro _dropfp fp, offset = 0
+.macro _dropfp fp, offset=0
.if \offset == 0
- mov R_sp(r), \fp
+ mov SP, \fp
#if __ELF__
- .cfi_def_cfa_register R_sp(r)
+ .cfi_def_cfa_register SP
#endif
.else
- lea R_sp(r), [\fp - \offset]
+ lea SP, [\fp - \offset]
#if __ELF__
- .cfi_def_cfa_register R_sp(r)
+ .cfi_def_cfa_register SP
.cfi_adjust_cfa_offset +\offset
#endif
.endif
.endm
.macro stalloc n
- sub R_sp(r), \n
+ sub SP, \n
#if __ELF__
.cfi_adjust_cfa_offset +\n
#endif
.endm
.macro stfree n
- add R_sp(r), \n
+ add SP, \n
#if __ELF__
.cfi_adjust_cfa_offset -\n
#endif
.endm
.macro savexmm r, offset
- movdqa [R_sp(r) + \offset], \r
+ movdqa [SP + \offset], \r
#if ABI_WIN && CPUFAM_AMD64
.seh_savexmm \r, \offset
#endif
.endm
.macro rstrxmm r, offset
- movdqa \r, [R_sp(r) + \offset]
+ movdqa \r, [SP + \offset]
.endm
.macro endprologue
#endif
-#if CPUFAM_X86
-
-.macro _reg.0
- // Stash GP registers and establish temporary stack frame.
- pushfd
- push eax
- push ecx
- push edx
- push ebp
- mov ebp, esp
- and esp, ~15
- sub esp, 512
- fxsave [esp]
-.endm
-
-.macro _reg.1
-.endm
-
-.macro _reg.2
-.endm
-
-.macro _reg.3 fmt
- // Print FMT and the other established arguments.
- lea eax, .L$_reg$msg.\@
- push eax
- call printf
- jmp .L$_reg$cont.\@
-.L$_reg$msg.\@:
- .ascii ";; \fmt\n\0"
-.L$_reg$cont.\@:
- mov eax, ebp
- and eax, ~15
- sub eax, 512
- fxrstor [eax]
- mov esp, ebp
- pop ebp
- pop edx
- pop ecx
- pop eax
- popfd
-.endm
-
-.macro msg msg
- _reg.0
- _reg.1
- _reg.2
- _reg.3 "\msg"
-.endm
-
-.macro reg r, msg
- _reg.0
- .ifeqs "\r", "esp"
- lea eax, [ebp + 20]
- push eax
- .else
- .ifeqs "\r", "ebp"
- push [ebp]
- .else
- push \r
- .endif
- .endif
- _reg.1
- _reg.2
- _reg.3 "\msg: \r = %08x"
-.endm
-
-.macro xmmreg r, msg
- _reg.0
- _reg.1
- _reg.2
- movdqu xmm0, \r
- pshufd xmm0, xmm0, 0x1b
- sub esp, 16
- movdqa [esp], xmm0
- _reg.3 "\msg: \r = %08x %08x %08x %08x"
-.endm
-
-.macro mmreg r, msg
- _reg.0
- _reg.1
- _reg.2
- pshufw \r, \r, 0x4e
- sub esp, 8
- movq [esp], \r
- _reg.3 "\msg: \r = %08x %08x"
-.endm
-
-.macro freg i, msg
- _reg.0
- _reg.1
- _reg.2
- finit
- fldt [esp + 32 + 16*\i]
- sub esp, 12
- fstpt [esp]
- _reg.3 "\msg: st(\i) = %.20Lg"
-.endm
-
-.macro fxreg i, msg
- _reg.0
- _reg.1
- _reg.2
- finit
- fldt [esp + 32 + 16*\i]
- sub esp, 12
- fstpt [esp]
- _reg.3 "\msg: st(\i) = %La"
-.endm
-
-#endif
-
///--------------------------------------------------------------------------
/// ARM-specific hacking.
#if WANT_PIC
ldr\cond \reg, .L$_leaextq$\@
.L$_leaextq_pc$\@:
- .if .L$_pcoff == 8
+ .if .L$_pcoff == 8
ldr\cond \reg, [pc, \reg]
- .else
+ .else
add\cond \reg, pc
ldr\cond \reg, [\reg]
- .endif
+ .endif
_LIT
.balign 4
.L$_leaextq$\@:
#endif
.endm
+.macro vzero vz=q15
+ // Set VZ (default q15) to zero.
+ vmov.u32 \vz, #0
+.endm
+
+.macro vshl128 vd, vn, nbit, vz=q15
+ // Set VD to VN shifted left by NBIT. Assume VZ (default q15) is
+ // all-bits-zero. NBIT must be a multiple of 8.
+ .if \nbit&3 != 0
+ .error "shift quantity must be whole number of bytes"
+ .endif
+ vext.8 \vd, \vz, \vn, #16 - (\nbit >> 3)
+.endm
+
+.macro vshr128 vd, vn, nbit, vz=q15
+ // Set VD to VN shifted right by NBIT. Assume VZ (default q15) is
+ // all-bits-zero. NBIT must be a multiple of 8.
+ .if \nbit&3 != 0
+ .error "shift quantity must be whole number of bytes"
+ .endif
+ vext.8 \vd, \vn, \vz, #\nbit >> 3
+.endm
+
// Apply decoration decor to register name reg.
#define _REGFORM(reg, decor) _GLUE(_REGFORM_, reg)(decor)
// Internal macros: `_REGFORM_r(decor)' applies decoration decor to register
// name r.
+#define _REGFORM_nil(decor) nil
+
#define _REGFORM_s0(decor) _DECOR(s, decor, 0)
#define _REGFORM_s1(decor) _DECOR(s, decor, 1)
#define _REGFORM_s2(decor) _DECOR(s, decor, 2)
#define QQ(qlo, qhi) D0(qlo)-D1(qhi)
// Stack management and unwinding.
-.macro setfp fp, offset = 0
+.macro setfp fp=r11, offset=0
.if \offset == 0
mov \fp, sp
.setfp \fp, sp
.L$_frameptr_p = -1
.endm
-.macro _dropfp fp, offset = 0
+.macro _dropfp fp, offset=0
.if \offset == 0
mov sp, \fp
.else
.endm
.macro pushreg rr:vararg
- stmfd sp!, {\rr}
+ push {\rr}
.save {\rr}
.endm
.macro popreg rr:vararg
- ldmfd sp!, {\rr}
+ pop {\rr}
.endm
.macro pushvfp rr:vararg
#endif
.endm
+.macro vzero vz=v31
+ // Set VZ (default v31) to zero.
+ dup \vz\().4s, wzr
+.endm
+
+.macro vshl128 vd, vn, nbit, vz=v31
+ // Set VD to VN shifted left by NBIT. Assume VZ (default v31) is
+ // all-bits-zero. NBIT must be a multiple of 8.
+ .if \nbit&3 != 0
+ .error "shift quantity must be whole number of bytes"
+ .endif
+ ext \vd\().16b, \vz\().16b, \vn\().16b, #16 - (\nbit >> 3)
+.endm
+
+.macro vshr128 vd, vn, nbit, vz=v31
+ // Set VD to VN shifted right by NBIT. Assume VZ (default v31) is
+ // all-bits-zero. NBIT must be a multiple of 8.
+ .if \nbit&3 != 0
+ .error "shift quantity must be whole number of bytes"
+ .endif
+ ext \vd\().16b, \vn\().16b, \vz\().16b, #\nbit >> 3
+.endm
+
// Stack management and unwinding.
-.macro setfp fp, offset = 0
+.macro setfp fp=x29, offset=0
// If you're just going through the motions with a fixed-size stack frame,
// then you want to say `add x29, sp, #OFFSET' directly, which will avoid
// pointlessly restoring sp later.
.L$_frameptr_p = -1
.endm
-.macro _dropfp fp, offset = 0
+.macro _dropfp fp, offset=0
.if \offset == 0
mov sp, \fp
.cfi_def_cfa_register sp
.cfi_adjust_cfa_offset -\n
.endm
-.macro pushreg x, y=
- .ifeqs "\y", ""
+.macro pushreg x, y=nil
+ .ifeqs "\y", "nil"
str \x, [sp, #-16]!
.cfi_adjust_cfa_offset +16
.cfi_rel_offset \x, 0
.endif
.endm
-.macro popreg x, y=
- .ifeqs "\y", ""
+.macro popreg x, y=nil
+ .ifeqs "\y", "nil"
ldr \x, [sp], #16
.cfi_restore \x
.cfi_adjust_cfa_offset -16
.endif
.endm
-.macro savereg x, y, z=
- .ifeqs "\z", ""
- str \x, [sp, #\y]
+.macro savereg x, y, z=nil
+ .ifeqs "\z", "nil"
+ str \x, [sp, \y]
.cfi_rel_offset \x, \y
.else
stp \x, \y, [sp, #\z]
.endif
.endm
-.macro rstrreg x, y, z=
- .ifeqs "\z", ""
- ldr \x, [sp, #\y]
+.macro rstrreg x, y, z=nil
+ .ifeqs "\z", "nil"
+ ldr \x, [sp, \y]
.cfi_restore \x
.else
ldp \x, \y, [sp, #\z]
#endif
#ifndef F
-# define F(name) name
+# ifdef SYM_USCORE
+# define F(name) _##name
+# else
+# define F(name) name
+# endif
#endif
#ifndef TYPE_FUNC
~mdw / catacomb / blobdiff