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Release 2.2.3.
[catacomb]
/
base
/
dispatch.c
diff --git
a/base/dispatch.c
b/base/dispatch.c
index
1b0ab2b
..
51619d5
100644
(file)
--- a/
base/dispatch.c
+++ b/
base/dispatch.c
@@
-47,6
+47,7
@@
# define CPUID1D_SSE2 (1u << 26)
# define CPUID1D_FXSR (1u << 24)
# define CPUID1C_AESNI (1u << 25)
# define CPUID1D_SSE2 (1u << 26)
# define CPUID1D_FXSR (1u << 24)
# define CPUID1C_AESNI (1u << 25)
+# define CPUID1C_RDRAND (1u << 30)
struct cpuid { unsigned a, b, c, d; };
struct cpuid { unsigned a, b, c, d; };
@@
-359,6
+360,7
@@
static void probe_hwcaps(void)
#define CAP__SWITCH(type, ubranch, slot) \
case type: probed.slot = a->value.ubranch; break;
WANTAUX(CAP__SWITCH)
#define CAP__SWITCH(type, ubranch, slot) \
case type: probed.slot = a->value.ubranch; break;
WANTAUX(CAP__SWITCH)
+ case AT_NULL: goto clean;
}
}
}
}
@@
-515,10
+517,12
@@
int cpu_feature_p(int feat)
CASE_CPUFEAT(X86_AESNI, "x86:aesni",
xmm_registers_available_p() &&
cpuid_features_p(CPUID1D_SSE2, CPUID1C_AESNI));
CASE_CPUFEAT(X86_AESNI, "x86:aesni",
xmm_registers_available_p() &&
cpuid_features_p(CPUID1D_SSE2, CPUID1C_AESNI));
+ CASE_CPUFEAT(X86_RDRAND, "x86:rdrand",
+ cpuid_features_p(0, CPUID1C_RDRAND));
#endif
#ifdef CAPMAP
# define FEATP__CASE(feat, tok) \
#endif
#ifdef CAPMAP
# define FEATP__CASE(feat, tok) \
- CASE_CPUFEAT(feat, tok, get_hwcaps & HF_##feat)
+ CASE_CPUFEAT(feat, tok, get_hwcaps
()
& HF_##feat)
CAPMAP(FEATP__CASE)
#undef FEATP__CASE
#endif
CAPMAP(FEATP__CASE)
#undef FEATP__CASE
#endif