/// -*- mode: asm; asm-comment-char: ?/ -*-
///
/// Fancy SIMD implementation of Salsa20 for ARM
///
/// (c) 2016 Straylight/Edgeware
///

///----- Licensing notice ---------------------------------------------------
///
/// This file is part of Catacomb.
///
/// Catacomb is free software; you can redistribute it and/or modify
/// it under the terms of the GNU Library General Public License as
/// published by the Free Software Foundation; either version 2 of the
/// License, or (at your option) any later version.
///
/// Catacomb is distributed in the hope that it will be useful,
/// but WITHOUT ANY WARRANTY; without even the implied warranty of
/// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
/// GNU Library General Public License for more details.
///
/// You should have received a copy of the GNU Library General Public
/// License along with Catacomb; if not, write to the Free
/// Software Foundation, Inc., 59 Temple Place - Suite 330, Boston,
/// MA 02111-1307, USA.

///--------------------------------------------------------------------------
/// Preliminaries.

#include "config.h"
#include "asm-common.h"

	.arch	armv7-a
	.fpu	neon

	.text

///--------------------------------------------------------------------------
/// Main code.

FUNC(salsa20_core_arm_neon)

	// Arguments are in registers.
	// r0 is the number of rounds to perform
	// r1 points to the input matrix
	// r2 points to the output matrix

	// First job is to slurp the matrix into the SIMD registers.  The
	// words have already been permuted conveniently to make them line up
	// better for SIMD processing.
	//
	// The textbook arrangement of the matrix is this.
	//
	//	[C K K K]
	//	[K C N N]
	//	[T T C K]
	//	[K K K C]
	//
	// But we've rotated the columns up so that the main diagonal with
	// the constants on it end up in the first row, giving something more
	// like
	//
	//	[C C C C]
	//	[K T K K]
	//	[T K K N]
	//	[K K N K]
	//
	// so the transformation looks like this:
	//
	//	[ 0  1  2  3]		[ 0  5 10 15] (a, q8)
	//	[ 4  5  6  7]    -->	[ 4  9 14  3] (b, q9)
	//	[ 8  9 10 11]		[ 8 13  2  7] (c, q10)
	//	[12 13 14 15]		[12  1  6 11] (d, q11)
	//
	// We need a copy for later.  Rather than waste time copying them by
	// hand, we'll use the three-address nature of the instruction set.
	// But this means that the main loop is offset by a bit.
	vldmia	r1, {QQ(q12, q15)}

	// Apply a column quarterround to each of the columns simultaneously,
	// moving the results to their working registers.  Alas, there
	// doesn't seem to be a packed word rotate, so we have to synthesize
	// it.

	// b ^= (a + d) <<<  7
	vadd.u32 q0, q12, q15
	vshl.u32 q1, q0, #7
	vsri.u32 q1, q0, #25
	veor	q9, q13, q1

	// c ^= (b + a) <<<  9
	vadd.u32 q0, q9, q12
	vshl.u32 q1, q0, #9
	vsri.u32 q1, q0, #23
	veor	q10, q14, q1

	// d ^= (c + b) <<< 13
	vadd.u32 q0, q10, q9
	 vext.32 q9, q9, q9, #3
	vshl.u32 q1, q0, #13
	vsri.u32 q1, q0, #19
	veor	q11, q15, q1

	// a ^= (d + c) <<< 18
	vadd.u32 q0, q11, q10
	 vext.32 q10, q10, q10, #2
	 vext.32 q11, q11, q11, #1
	vshl.u32 q1, q0, #18
	vsri.u32 q1, q0, #14
	veor	q8, q12, q1

0:
	// The transpose conveniently only involves reordering elements of
	// individual rows, which can be done quite easily, and reordering
	// the rows themselves, which is a trivial renaming.  It doesn't
	// involve any movement of elements between rows.
	//
	//	[ 0  5 10 15]		[ 0  5 10 15] (a, q8)
	//	[ 4  9 14  3]	 -->	[ 1  6 11 12] (b, q11)
	//	[ 8 13	2  7]		[ 2  7	8 13] (c, q10)
	//	[12  1	6 11]		[ 3  4	9 14] (d, q9)
	//
	// The reorderings have been pushed upwards to reduce delays.

	// Apply the row quarterround to each of the columns (yes!)
	// simultaneously.

	// b ^= (a + d) <<<  7
	vadd.u32 q0, q8, q9
	vshl.u32 q1, q0, #7
	vsri.u32 q1, q0, #25
	veor	q11, q11, q1

	// c ^= (b + a) <<<  9
	vadd.u32 q0, q11, q8
	vshl.u32 q1, q0, #9
	vsri.u32 q1, q0, #23
	veor	q10, q10, q1

	// d ^= (c + b) <<< 13
	vadd.u32 q0, q10, q11
	 vext.32 q11, q11, q11, #3
	vshl.u32 q1, q0, #13
	vsri.u32 q1, q0, #19
	veor	q9, q9, q1

	// a ^= (d + c) <<< 18
	vadd.u32 q0, q9, q10
	 vext.32 q10, q10, q10, #2
	 vext.32 q9, q9, q9, #1
	vshl.u32 q1, q0, #18
	vsri.u32 q1, q0, #14
	veor	q8, q8, q1

	// We had to undo the transpose ready for the next loop.  Again, push
	// back the reorderings to reduce latency.  Decrement the loop
	// counter and see if we should go round again.
	subs	r0, r0, #2
	bls	9f

	// Do the first half of the next round because this loop is offset.

	// b ^= (a + d) <<<  7
	vadd.u32 q0, q8, q11
	vshl.u32 q1, q0, #7
	vsri.u32 q1, q0, #25
	veor	q9, q9, q1

	// c ^= (b + a) <<<  9
	vadd.u32 q0, q9, q8
	vshl.u32 q1, q0, #9
	vsri.u32 q1, q0, #23
	veor	q10, q10, q1

	// d ^= (c + b) <<< 13
	vadd.u32 q0, q10, q9
	 vext.32 q9, q9, q9, #3
	vshl.u32 q1, q0, #13
	vsri.u32 q1, q0, #19
	veor	q11, q11, q1

	// a ^= (d + c) <<< 18
	vadd.u32 q0, q11, q10
	 vext.32 q10, q10, q10, #2
	 vext.32 q11, q11, q11, #1
	vshl.u32 q1, q0, #18
	vsri.u32 q1, q0, #14
	veor	q8, q8, q1

	b	0b

	// Almost there.  Firstly the feedfoward addition.  Also, establish a
	// constant which will be useful later.
9:	vadd.u32 q0, q8, q12			//  0,  5, 10, 15
	 vmov.i64 q12, #0xffffffff		// = (0, -1; 0, -1)
	vadd.u32 q1, q9, q13			//  4,  9, 14,  3
	vadd.u32 q2, q10, q14			//  8, 13,  2,  7
	vadd.u32 q3, q11, q15			// 12,  1,  6, 11

	// Next we must undo the permutation which was already applied to the
	// input.  The core trick is from Dan Bernstein's `armneon3'
	// implementation, but with a lot of liposuction.
	vmov	q15, q0

	// Sort out the columns by pairs.
	vbif	q0, q3, q12			//  0,  1, 10, 11
	vbif	q3, q2, q12			// 12, 13,  6,  7
	vbif	q2, q1, q12			//  8,  9,  2,  3
	vbif	q1, q15, q12			//  4,  5, 14, 15

	// Now fix up the remaining discrepancies.
	vswp	D1(q0), D1(q2)
	vswp	D1(q1), D1(q3)

	// And with that, we're done.
	vstmia	r2, {QQ(q0, q3)}
	bx	r14

ENDFUNC

///----- That's all, folks --------------------------------------------------